ADE7758ARW Analog Devices Inc, ADE7758ARW Datasheet - Page 58

• Manufacturer Part Number: ADE7758ARW
• Description: IC ENERGY METERING 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7758ARW

• Rohs Status: RoHS non-compliant
• Input Impedance: 380 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 8mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• Lead Free Status / RoHS Status: Not Compliant

ADE7758
As explained earlier, the data write is initiated by a write to the
communications register followed by the data. During a data
write operation to the ADE7758, data is transferred to all on-
chip registers one byte at a time. After a byte is transferred into
the serial port, there is a finite time duration before the content
in the serial port buffer is transferred to one of the ADE7758
on-chip registers. Although another byte transfer to the serial
port can start while the previous byte is being transferred to the
destination register, this second-byte transfer should not finish
until at least 900 ns after the end of the previous byte transfer.
This functionality is expressed in the timing specification t
Figure 91). If a write operation is aborted during a byte transfer
( CS brought high), then that byte is not written to the
destination register.
SCLK
DOUT
SCLK
DIN
DIN
CS
CS
SCLK
DIN
t
t
1
1
1
0
X
A6
A6
t
2
X
A5
A5
t
3
COMMAND BYTE
COMMAND BYTE
MOST SIGNIFICANT BYTE
A4
X
A4
t
4
A3
A3
X
t
5
DB11
A2
A2
Figure 91. Serial Interface Write Timing Diagram
Figure 93. Serial Interface Read Timing Diagram
Figure 92. 12-Bit Serial Write Operation
A1
DB10
A1
A0
6
A0
DB9
(see
Rev. D | Page 58 of 72
t
t
t
7
DB8
9
11
DB7
DB7
DB7
MOST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE
Destination registers can be up to 3 bytes wide (see the
Accessing the On-Chip Registers section). Therefore, the first
byte shifted into the serial port at DIN is transferred to the most
significant byte (MSB) of the destination register. If the
destination register is 12 bits wide, for example, a two-byte data
transfer must take place. The data is always assumed to be right
justified; therefore, in this case, the four MSBs of the first byte
would be ignored, and the four LSBs of the first byte written to
the ADE7758 would be the four MSBs of the 12-bit word.
Figure 92 illustrates this example.
DB6
DB5
LEAST SIGNIFICANT BYTE
DB4
DB0
DB0
DB3
t
t
7
10
DB2
LEAST SIGNIFICANT BYTE
DB7
LEAST SIGNIFICANT BYTE
DB7
DB1
t
6
DB0
t
12
DB0
DB0
t
13
t
8