ADE7753ARSZ Analog Devices Inc, ADE7753ARSZ Datasheet - Page 56

IC ENERGY METERING 1PHASE 20SSOP

ADE7753ARSZ

Manufacturer Part Number
ADE7753ARSZ
Description
IC ENERGY METERING 1PHASE 20SSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADE7753ARSZ

Input Impedance
390 KOhm
Measurement Error
0.1%
Voltage - I/o High
2.4V
Voltage - I/o Low
0.8V
Current - Supply
3mA
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SSOP (0.200", 5.30mm Width)
Meter Type
Single Phase
Ic Function
Single-Phase Multifunction Metering IC
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
SSOP
No. Of Pins
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADE7753ZEB - BOARD EVALUATION AD7753
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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ADE7753
INTERRU
RESET IN
INTER
The status register is used by the MCU to
ADE7753, the corresponding flag in the i
enable register, the IRQ
interrupt status register to determine the
Table 13. Interrupt Status Register, Rese
Bit
L
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ocation
RUP
(CHANNEL 2 SAMPLE ABOVE VPKLVL)
(CHANNEL 1 SAMPLE ABOVE IPKLVL)
P
T
ERRUPT S
T STATUS
T ENABLE EGI
Interru
Flag
AEHF
SAG
CYCEND
WSMP
ZX
TEMP
RESET
AEOF
PKV
PKI
VAEHF
VAEOF
ZXTO
PPOS
PNEG
RESERVED
(POWER POSITIVE TO NEGATIVE)
(POWER NEGATIVE TO POSITIVE)
(ZERO-CROSSING TIMEOUT)
(VAENERGY IS HALF-FULL)
(VAENERGY OVERFLOW)
pt
logic output goes active low. When the MCU services the i
TA
R
R
EGISTER
Description
Indicates that an interrupt was caused by the 0-to-1 transition of the MSB of the active energy register, i.e., the
AENERGY register is half full.
Indicates that an interrupt was caused by a SAG on the line voltage.
Indicates the end of energy accumulation over an integer number of half line cycles as defined by the content
of the LINECYC register—see the Line Cycle Energy Accumulation Mode section.
Indicates that new data is present in the waveform register.
This status bit reflects the status of the ZX logic ouput—see the Zero-Crossing Detection section.
Indicates that a temperature conversion result is available in the temperature register.
Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has no
function in the interrupt enable register, i.e., this status bit is set at the end of a reset, but it cannot be enabled
to cause an interrupt.
Indicates that the active energy register has overflowed.
Indicates that waveform sample from Channel 2 has exceeded the VPKLVL value.
Indicates that waveform sample from Channel 1 has exceeded the IPKLVL value.
Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the apparent energy register, i.e.,
the VAENERGY register is half full.
Indicates that the apparent energy register has overflowed.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the specified number
of line cycles—see the Zero-Crossing Timeout section.
Indicates that the power has gone from negative to positive.
Indicates that the power has gone from positive to negative.
Reserved.
TUS R
RESERVED
STER (0
VAEOF
VAEHF
PNEG
PPOS
ZXTO
EGI
PKV
PK1
(0
STER (0x0C)
nte
sou
t In
x0B),
x0A)
determine th
rrupt status register i
15 14 13 12 11 10
rce of the interrupt.
0
terrupt Status Register, and Interrup
Figure 96. Interrupt Status/Interrupt Enable Register
0
0
0
e source o
,
0
0
Rev. A | Page 56 of 60
9
0
f an inter
s se
8
0
t to logic high
7
0
6
0
rupt req
5
0
4
0
3
0
nter
uest ( IRQ ). When an interrupt event occurs
. If the ena
t Enable Register
2
0
rupt, it must first carry out a read from the
1
0
0
0
ADDR: 0x0A, 0x0B, 0x0C
ble bit for this flag is Logic 1 in th
AEHF
(ACTIVE ENERGY HALF-FULL)
SAG
(SAG ONLINE VOLTAGE)
CYCEND
(END OF LINECYC HALF LINE CYCLES)
WSMP
(WAVEFORM SAMPLES DATA READY)
ZX
(ZERO CROSSING)
TEMPL
(TEMPERATURE DATA READY)
RESET
(END OF SOFTWARE/HARDWARE RESET)
AEOF
(ACTIVE ENERGY REGISTER OVERFLOW)
02875-A-013
in the
e interrupt

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