CY14B101K-SP35XIT Cypress Semiconductor Corp, CY14B101K-SP35XIT Datasheet - Page 4

• Manufacturer Part Number: CY14B101K-SP35XIT
• Description: IC NVSRAM 1MBIT 35NS 48SSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY14B101K-SP35XIT

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Operation
The CY14B101K nvSRAM consists of two functional compo-
nents paired in the same physical cell. The components are
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM READ and WRITE operations are inhibited. The
CY14B101K suppots infinite reads and writes similar to a typical
SRAM. In addition, it provides infinite RECALL operations from
the nonvolatile cells and up to 200K STORE operations.
See the
complete description of read and write modes.
SRAM READ
The CY14B101K performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
accessed. When the READ is initiated by an address transition,
the outputs are valid after a delay of t
18). If the READ is initiated by CE or OE, the outputs are valid at
t
data outputs repeatedly respond to address changes within the
t
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable before entering
the WRITE cycle and must remain stable until either CE or WE
go HIGH at the end of the cycle. The data on the common I/O
pins DQ
before the end of a WE controlled WRITE or before the end of
an CE controlled WRITE. Keep OE HIGH during the entire
WRITE cycle to avoid data bus contention on common I/O lines.
If OE is left LOW, internal circuitry turns off the output buffers
t
AutoStore
The CY14B101K stores data to nvSRAM using one of three
storage operations:
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101K.
During normal operations, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
Document Number: 001-06401 Rev. *J
1. Hardware Store activated by HSB
2. Software Store activated by an address sequence
3. AutoStore on device power down
ACE
AA
HZWE
access time without the need for transitions on any control
or at t
after WE goes LOW.
0–7
“Truth Table For SRAM Operations”
0-16
DOE
®
is written into the memory if the data is valid t
, whichever is later (see
determines which of the 131,072 data bytes are
Operation
CC
pin drops below V
AA
Figure 9
(see
CAP
Figure 8
on page 23 for a
on page 18). The
SWITCH
pin. This stored
, the part
on page
CC
SD
to
automatically disconnects the V
operation is initiated with power provided by the V
Figure 2. AutoStore Mode
Figure 2
(V
Characteristics
on the V
chip. A pull up should be placed on WE to hold it inactive during
power up. This pull up is only effective if the WE signal is tri-state
during power up. Many MPUs tri-state their controls on power up.
Verify this when using the pull up. When the nvSRAM comes out
of power-on-recall, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation takes place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a WRITE operation took place. Monitor the
HSB signal by the system to detect if an AutoStore cycle is in
progress.
Hardware STORE (HSB) Operation
The CY14B101K provides the HSB pin for controlling and
acknowledging the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B101K conditionally initiates a STORE operation
after t
the SRAM has taken place since the last STORE or RECALL
cycle. The HSB pin also acts as an open drain driver that is inter-
nally driven LOW to indicate a busy condition while the STORE
(initiated by any means) is in progress. This pin is externally
pulled up if it is used to drive other inputs.
CAP
) for automatic store operation. Refer to
DELAY
CAP
shows the proper connection of the storage capacitor
. An actual STORE cycle only begins if a WRITE to
pin is driven to 5V by a charge pump internal to the
on page 16 for the size of the V
V
CAP
CAP
pin from V
V
WE
CC
CY14B101K
CAP
CC
CAP
DC Electrical
. The voltage
Page 4 of 29
V
. A STORE
CC
capacitor.
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