CY14B101K-SP35XIT Cypress Semiconductor Corp, CY14B101K-SP35XIT Datasheet - Page 15

• Manufacturer Part Number: CY14B101K-SP35XIT
• Description: IC NVSRAM 1MBIT 35NS 48SSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY14B101K-SP35XIT

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. Register Map Detail (continued)
Document Number: 001-06401 Rev. *J
0x1FFF4
0x1FFF3
0x1FFF2
0x1FFF1
0x1FFF0
OSCF
WDF
CAL
AF
PF
W
M
M
M
R
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit
to ignore the hours value.
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1 causes the match
circuit to ignore the minutes value.
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to 1 causes the match
circuit to ignore the seconds value.
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains
the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.
Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset
by the user. It is cleared to 0 when the Flags register is read or on power-up.
Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the
match bits = 0. It is cleared when the Flags register is read or on power-up.
Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold V
0 when the Flags register is read or on power-up.
Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation. This
indicates that RTC backup power failed and clock value is no longer valid. The user must reset this bit to 0 to clear this
condition (Flag). The chip does not clear this flag. This bit survives power cycles.
Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes
normal operation. This bit defaults to 0 (disabled) on power up.
Write Enable: Setting the W bit to 1 freezes updates of the RTC registers. The user can then write to RTC registers,
Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents of
the RTC registers to be transferred to the time keeping counters if the time has been changed (a new base time is
loaded). This bit defaults to 0 on power up.
Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates are not seen during
the reading process. Set R bit to 0 to resume clock updates to the holding register. Setting this bit does not require W
bit to be set to 1. This bit defaults to 0 on power up.
WDF
D7
D7
D7
D7
D7
M
M
M
D6
D6
D6
D6
D6
AF
10s Centuries
10s Alarm Seconds
10s Alarm Minutes
10s Alarm Hours
D5
D5
D5
D5
D5
PF
Time Keeping - Centuries
OSCF
Alarm - Seconds
Alarm - Minutes
D4
D4
D4
D4
D4
Alarm - Hours
Flags
D3
D3
D3
D3
D3
0
CAL
D2
D2
D2
D2
D2
Alarm Seconds
Alarm Minutes
Alarm Hours
Centuries
D1
D1
D1
D1
D1
W
SWITCH
CY14B101K
. It is cleared to
Page 15 of 29
D0
D0
D0
D0
D0
R
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