PSD834F2-70J STMicroelectronics, PSD834F2-70J Datasheet - Page 70

• Manufacturer Part Number: PSD834F2-70J
• Description: IC FLASH 2MBIT 70NS 52PLCC
• Manufacturer: STMicroelectronics

Specifications of PSD834F2-70J

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2004-5

PSD813F2V, PSD854F2V
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG signals (TMS, TCK,
TDI, and TDO). They are used to speed Program
and Erase cycles by indicating status on PSD sig-
nals instead of having to scan the status out seri-
ally using the standard JTAG channel. See
Application Note AN1153.
TERR indicates if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until an
“ISC_CLEAR” command is executed or a chip Re-
set
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy de-
scribed in the section entitled
(PC3), page
vice is in READ Mode (primary and secondary
Flash memory contents can be read). TSTAT is
Low when Flash memory Program or Erase cycles
are in progress, and also when data is being writ-
ten to the secondary Flash memory.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com-
mand. This facilitates a wired-OR connection of
TSTAT signals from multiple PSD devices and a
wired-OR connection of TERR signals from those
same devices. This is useful when several PSD
devices are “chained” together in a JTAG environ-
ment.
70/109
(RESET)
20. TSTAT is High when the PSD de-
pulse
is
received
Ready/Busy
after
Doc ID 10552 Rev 3
an
Security and Flash memory Protection
When the security bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Security Bit can be
set in PSDsoft Express Configuration.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The sector protect bits can be set in PSD-
soft Express Configuration.
Table 34. JTAG Port Signals
PC0
PC1
PC3
PC4
PC5
PC6
Port C Pin
TMS
TCK
TSTAT
TERR
TDI
TDO
JTAG Signals
Mode Select
Clock
Status
Error Flag
Serial Data In
Serial Data Out
Description