PSD834F2-15J STMicroelectronics, PSD834F2-15J Datasheet
PSD834F2-15J
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PSD834F2-15J Summary of contents
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... Erase/WRITE Cycles of PLD ® ■ Packages are ECOPACK January 2009 This is information on a product still in production but not recommended for new designs. 3.3 V supply Flash PSD for 8-bit MCUs Figure 1. Packages Rev 3 PSD834F2V NOT FOR NEW DESIGN PQFP52 (M) PLCC52 (J) 1/95 ...
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... PSD834F2V TABLE OF CONTENTS SUMMARY DESCRIPTION KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Page Register PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MCU Bus Interface JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 In-System Programming (ISP Power Management Unit (PMU DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSD REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DETAILED OPERATION MEMORY BLOCKS Primary Flash Memory and Secondary Flash memory Description ...
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... JTAG In-System Programming (ISP Port Configuration Registers (PCR Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Port D Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Port D Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PLD Power Management PSD Chip Select Input (CSI, PD2 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 PSD834F2V 3/95 ...
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... PSD834F2V RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Reset of Flash Memory Erase and Program Cycles PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 63 Standard JTAG Signals JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Security and Flash memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 INITIAL DELIVERY STATE AC/DC PARAMETERS ...
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... PSD. Code examples are also provided for: – Flash memory IAP via the UART of the host MCU – Memory paging to execute code across several PSD memory pages – Loading, reading, and manipulation of PSD macrocells by the MCU. PSD834F2V 5/95 ...
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... PSD834F2V KEY FEATURES ■ A simple interface to 8-bit microcontrollers that use either multiplexed or non-multiplexed busses. The bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a READ or WRITE is performed. A partial list of the MCU families supported include: – ...
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... Figure 2. PSD Block Diagram PSD834F2V AI05793b 7/95 ...
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... PSD834F2V PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 2 shows the architecture of the PSD device family. The functions of each block are de- scribed briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discus- sion can be found in the section entitled “ ...
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... Table 2. JTAG SIgnals on Port C Port C Pins PC0 PC1 PC3 PC4 PC5 PC6 JTAG Programming Device Programmer Yes Yes Yes Yes Yes Yes Yes Yes PSD834F2V JTAG Signal TMS TCK TSTAT TERR TDI TDO IAP Yes Yes No No 9/95 ...
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... PSD834F2V DEVELOPMENT SYSTEM The PSD family is supported by PSDsoft Express, a Windows-based software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 3 ...
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... If your MCU does not output a Program Select CNTL2 49 I Enable signal, this port can be used as a generic input. This port is connected to the PLDs. Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low Reset Power-up. Description PSD834F2V 11/95 ...
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... PSD834F2V Pin Name Pin Type These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O – write to or read from a standard output or input port. PA0 29 2. CPLD macrocell (McellAB0-7) outputs. PA1 28 3. Inputs to the PLDs. ...
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... CSIOP space is the 256 bytes of address that is al- located by the user to the internal PSD registers. Description 2 for the JTAG Serial Interface. 2 for the JTAG Serial Interface. Table 6 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description. PSD834F2V 13/95 ...
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... PSD834F2V Table 5. I/O Port Latched Address Output Assignments (Note 1) MCU 8051XA (8-bit) N/A 80C251 (page mode) N/A All other 8-bit multiplexed Address a3-a0 8-bit non-multiplexed bus N/A Note: 1. See the section entitled “I/O PORTS”, on page 46, on how to enable the Latched Address Output function. ...
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... MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a READ operation or polling Ready/Busy (PC3). Flash memory can also be read by using special instructions to retrieve particular Flash device in- formation (sector protect status and ID). PSD834F2V 15/95 ...
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... PSD834F2V Table 7. Instructions FS0-FS7 or Instruction CSBOOT0- Cycle 1 CSBOOT3 “Read” READ Read Main AAh X555h Flash ID Read Sector AAh@ 1 6,8,13 X555h Protection Program a AAh X555h Flash Byte Flash Sector AAh@ 1 7,13 X555h Erase Flash Bulk AAh X555h Erase Suspend B0h XXXXh ...
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... The sector protection status for all NVM blocks (primary Flash memory or secondary Flash mem- ory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O space. See the section entitled “Flash Memory Sector Pro- tect”, on page 22, for register definitions. PSD834F2V is below V . LKO primary 17/95 ...
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... PSD834F2V Reading the Erase/Program Status Bits. The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Pro- gram cycle of Flash memory. These status bits minimize the time that the MCU spends perform- ing these tasks and are defined in Table 8. The status bits can be read as many times as needed ...
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... PSDsoft Express generates ANSI C code func- tions which implement these Data Polling algo- rithms. Figure 4. Data Polling Flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 DQ7 YES = DATA NO FAIL PSD834F2V PASS AI01369B 19/95 ...
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... PSD834F2V Data Toggle. Checking the Toggle Flag (DQ6) Bit is a method of determining whether a Program or Erase cycle is in progress or has completed. Figure 5 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be pro- grammed in Flash memory to check status ...
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... Flash memory sector that was being erased is invalid. Resume Sector Erase Suspend Sector Erase instruction was previously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See Table 7.) PSD834F2V 21/95 ...
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... PSD834F2V Specific Features Flash Memory Sector Protect. Each and secondary Flash memory sector can be sepa- rately protected against Program and Erase cy- cles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated through the JTAG Port or a Device Programmer. ...
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... Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest. Figure 6. Priority Level of Memory and I/O Components Highest Priority Level 1 SRAM, I /O, or Peripheral I /O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority PSD834F2V AI02867D 23/95 ...
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... PSD834F2V Memory Select Configuration for MCUs with Separate Program and Data Spaces. The 8031 and compatible family of MCUs, which includes the 80C51, 80C151, 80C251, and 80C51XA, have separate address spaces for Program memory (selected using Program Select Enable (PSEN, CNTL2)) and Data memory (selected using Read Strobe (RD, CNTL1)) ...
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... VM REG BIT 2 VM REG BIT 0 Program and or Read Strobe (RD, CNTL1). For example, to configure the primary Flash memory in Combined space, Bits b2 and b4 of the VM register are set to 1 (see Figure 8). Primary RS0 Flash Memory CSBOOT0-3 FS0-FS7 CS OE PSD834F2V Secondary SRAM Flash Memory AI02870C 25/95 ...
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... PSD834F2V Page Register The 8-bit Page Register increases the addressing capability of the MCU by a factor 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0- PGR7) are inputs to the DPLD decoder and can be included in the ...
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... Port B Input PB7-PB0 Macrocells Port C Input PC7-PC0 Macrocells Port D Inputs PD2-PD0 Page Register PGR7-PGR0 Macrocell AB MCELLAB.FB7- Feedback FB0 Macrocell BC MCELLBC.FB7- Feedback FB0 Secondary Flash memory Program Ready/Busy Status Bit Note: 1. The address inputs are A19-A4 in 80C51XA mode. PSD834F2V Number of Signals 27/95 ...
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... PSD834F2V Figure 10. PLD Diagram 8 PAGE ATA REGISTER US DECODE PLD 73 OUTPUT MACROCELL FEEDBACK 16 CPLD 73 DIRECT MACROCELL INPUT TO MCU DATA BUS INPUT MACROCELL & INPUT PORTS 24 3 PORT D INPUTS 28/95 8 PRIMARY FLASH MEMORY SELECTS 4 SECONDARY NON-VOLATILE MEMORY SELECTS 1 SRAM SELECT 1 CSIOP SELECT 2 PERIPHERAL SELECTS ...
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... CSIOP Select (PSD Configuration Register) signal ■ 1 JTAG Select signal (enables JTAG on Port C) ■ 2 internal Peripheral Select signals (Peripheral I/O mode). (INPUTS) (24) (8) (8) (8) (16) (3) (1) (3) (1) (1) PSD834F2V CSBOOT 0 3 CSBOOT 1 3 CSBOOT 2 3 CSBOOT FS0 3 FS1 3 FS2 3 FS3 8 PRIMARY FLASH ...
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... PSD834F2V Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate three External Chip Se- lect (ECS0-ECS2), routed to Port D. ...
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... Figure 12. Macrocell and I/O Port BUS INPUT PLD MUX MUX ARRAY AND BUS INPUT PLD PSD834F2V MUX MUX 31/95 ...
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... PSD834F2V Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are con- nected to Ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as McellBC0-McellBC7 McellAB out- put is not assigned to a specific pin in PSDabel, the Macrocell Allocator block assigns it to either Port ...
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... Data can be loaded to the Output Macrocells (OMC) on the trailing edge of Write Strobe (WR, CNTL0) (edge loading) or during the time that Write Strobe (WR, CNTL0) is active (level load- ing). The method of loading is specified in PSDsoft Express Configuration. PSD834F2V 33/95 ...
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... PSD834F2V Figure 13. CPLD Output Macrocell 34/95 ARRAY AND BUS INPUT PLD ...
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... Master can then read the In- put Macrocells (IMC) directly. Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from the Slave MCU inputs Read Strobe (RD, CNTL1), Write Strobe (WR, CNTL0), and Slave_CS. PSD834F2V 35/95 ...
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... PSD834F2V Figure 14. Input Macrocell 36/95 ARRAY AND BUS INPUT PLD ...
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... Figure 15. Handshaking Communication Using Input Macrocells PSD834F2V 37/95 ...
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... PSD834F2V MCU BUS INTERFACE The “no-glue logic” MCU Bus Interface block can be directly connected to most popular MCUs and their control signals. Key 8-bit MCUs, with their bus types and control signals, are shown in Table 14. The interface type is specified using the PSD- soft Express Configuration ...
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... Figure 16. An Example of a Typical 8-bit Multiplexed Bus Interface MCU WR RD BHE ALE RESET PSD 15:8 ] PSD834F2V PORT A ( OPTIONAL ) ADIO PORT PORT B ( OPTIONAL ) WR ( CNTRL0 ) RD ( CNTRL1 ) BHE ( CNTRL2 ) PORT C RST ALE ( PD0 ) PORT D AI02878C 39/95 ...
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... PSD834F2V PSD Interface to a Non-Multiplexed 8-bit Bus. Figure 17 shows an example of a system using a MCU with an 8-bit non-multiplexed bus and a PSD. The address bus is connected to the ADIO Port, and the data bus is connected to Port A. Port tri-state mode when the PSD is not ac- cessed by the MCU ...
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... PSEN PSEN 30 ALE ALE/P 11 TXD 10 RXD RESET Connecting to PSD Pins CNTL0 CNTL1 CNTL2 CNTL0 CNTL1 CNTL0 CNTL1 CNTL0 CNTL1 CNTL2 PSD834F2V AD7-AD0 AD [ 7:0 ] PSD 29 30 ADIO0 PA0 31 28 ADIO1 PA1 32 27 ADIO2 PA2 33 25 ADIO3 PA3 34 24 PA4 ADIO4 23 35 ADIO5 ...
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... PSD834F2V The first configuration is 80C31 compatible, and the bus interface to the PSD is identical to that shown in Figure 18. The second and third configu- rations have the same bus connection as shown in Figure 17. There is only one Read Strobe (PSEN) connected to CNTL1 on the PSD. The A16 con- nection to PA0 allows for a larger address input to the PSD ...
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... AD10 P2.2 27 AD11 P2.3 28 AD12 P2.4 29 AD13 P2.5 30 AD14 P2.6 31 AD15 P2.7 ALE 33 ALE 32 RD PSEN PSEN RD/A16 RESET PSD834F2V PSD A0 30 ADIO0 A1 31 ADIO1 A2 32 ADIO2 A3 33 ADIO3 A4 34 ADIO4 A5 35 ADIO5 A6 36 ADIO6 A7 37 ADIO7 AD8 39 ADIO8 AD9 40 ADIO9 ...
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... PSD834F2V 80C51XA. The Philips 80C51XA MCU family sup- ports 16-bit multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multi- plexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11- A4) are multiplexed with data bits (D7-D0). ...
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... PC4 14 AD5 PC5 15 AD6 PC6 16 AD7 PC7 20 PD0 21 PD1 22 PD2 23 PD3 24 PD4 25 PD5 3 MODA RESET PSD834F2V AD7-AD0 AD7-AD0 PSD 30 29 ADIO0 PA0 31 28 ADIO1 PA1 27 32 PA2 ADIO2 33 25 ADIO3 PA3 34 24 AD104 PA4 35 23 AD105 PA5 36 22 PA6 ADIO6 37 21 ...
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... PSD834F2V I/O PORTS There are four programmable I/O ports: Ports and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Ex- press Configuration or by the MCU writing to on- chip registers in the CSIOP space ...
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... Mode. Note: Do not drive address signals with Address Out Mode to an external memory device in- tended for the MCU to Boot from the external de- vice. The MCU must first Boot from PSD memory so the Direction and Control register bits can be set. PSD834F2V 47/95 ...
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... PSD834F2V Table 18. Port Operating Modes Port Mode MCU I/O Yes PLD I/O McellAB Outputs Yes McellBC Outputs No Additional Ext. CS Outputs No PLD Inputs Yes Address Out Yes (A7 – 0) Address In Yes Data Port Yes (D7 – 0) Peripheral I/O Yes JTAG ISP No Note: 1. Can be multiplexed with other I/O functions. ...
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... In-System Programming (ISP) is not per- formed in normal Operating mode. For more infor- mation on the JTAG Port, see the section entitled “PROGRAMMING JTAG SERIAL INTERFACE”, on page 63. PSEL DATA BUS PSD834F2V Port B (PB7-PB4) N/A Address a15-a12 Address a7-a4 Address a7-a4 IN-CIRCUIT USING ...
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... PSD834F2V Port Configuration Registers (PCR) Each Port has a set of Port Configuration Regis- ters (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in Table 6. The addresses in Table 6 are the offsets in hexadecimal from the base of the CSIOP register ...
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... A,B,C WRITE – loading macrocells flip-flop WRITE/READ – prevents loading into a given A,B,C macrocell A,B,C READ – outputs of the Input Macrocells A,B,C READ – the output enable control of the port driver PSD834F2V Bit 2 Bit 1 Bit 0 Slew Slew Slew Rate Rate Rate ...
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... PSD834F2V Ports A and B – Functionality and Structure Ports A and B have similar functionality and struc- ture, as shown in Figure 24. The two ports can be configured to perform one or more of the following functions: ■ MCU I/O Mode ■ CPLD Output – Macrocells McellAB7-McellAB0 can be connected to Port A or Port B. McellBC7- McellBC0 can be connected to Port B or Port C. ■ ...
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... Control Register is required. Pin PC7 may be configured as the DBE input in certain MCU bus interfaces. DATA OUT REG. DATA OUT SPECIAL FUNCTION P D DATA IN B DIR REG PSD834F2V PORT C PIN OUTPUT MUX OUTPUT SELECT ENABLE OUT INPUT MACROCELL 1 SPECIAL FUNCTION CONFIGURATION BIT AI02888B 53/95 ...
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... PSD834F2V Port D – Functionality and Structure Port D has three I/O pins. See Figure 26 and Fig- ure 27. This port does not support Address Out mode, and therefore no Control Register is re- quired. Port D can be configured to perform one or more of the following functions: ■ MCU I/O Mode ■ ...
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... The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 27.) ENABLE (.OE) POLARITY BIT ENABLE (.OE) POLARITY BIT ENABLE (.OE) POLARITY BIT PSD834F2V DIRECTION REGISTER PD0 PIN ECS0 DIRECTION REGISTER PD1 PIN ECS1 DIRECTION REGISTER PD2 PIN ...
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... PSD834F2V POWER MANAGEMENT All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows: ■ All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design methodology, ...
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... Data Port Peripheral I/O DISABLE BUS INTERFACE PD CLR APD COUNTER PD Memory Access Access Recovery Time to Time 1 No Access ) PSD834F2V Pin Level No Change No Change Undefined Tri-State Tri-State EEPROM SELECT FLASH SELECT PLD SRAM SELECT POWER DOWN ( PDN ) SELECT Typical Standby Normal Access ...
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... PSD834F2V For Users of the HC11 (or compatible). The HC11 turns off its E clock when it sleeps. There- fore, if you are using an HC11 (or compatible) in your design, and you wish to use the Power-down mode, you must not connect the E clock to CLKIN (PD1). You should instead connect a crystal oscil- lator to CLKIN (PD1) ...
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... CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN (PD1) Powers-up the PLD when Turbo bit is 0. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. PSD834F2V 59/95 ...
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... PSD834F2V PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft Ex- press as PSD Chip Select Input (CSI). When Low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A ...
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... A Reset (RESET) also resets the internal Flash memory state machine. During a Flash memory . LKO Program or Erase cycle, Reset (RESET) termi- nates the cycle and returns the Flash memory to the READ Mode within a period OPR PSD834F2V period is needed before the OPR ramps up to operating level NLNH-A t NLNH ...
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... PSD834F2V Table 32. Status During Power-On Reset, Warm Reset and Power-down Mode Port Configuration MCU I/O Input mode Valid after internal PSD PLD Output configuration bits are loaded Address Out Tri-stated Data Port Tri-stated Peripheral I/O Tri-stated Register PMMR0 and PMMR2 Cleared to 0 ...
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... FlashLINK to program their PSD. Table 33. JTAG Port Signals Port C Pin PC0 PC1 PC3 PC4 PC5 to the PSD PC6 PSD834F2V or the microcontroller. the designer can write JTAG Signals Description TMS Mode Select TCK ...
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... PSD834F2V JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status on PSD sig- nals instead of having to scan the status out seri- ally using the standard JTAG channel ...
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... The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 31 shows the PLD mA/MHz as a function of the number of Product Terms (PT) used. ■ In the PLD timing parameters, add the required delay when Turbo Bit is '0 PSD834F2V PT 100 AI03100 65/95 ...
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... PSD834F2V Table 35. Example of PSD Typical Power Calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number of product terms used (from fitter report total product terms ...
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... Freq ALE + % PLD x (from graph using Freq PLD µA x 0.90 + 0.1 x (0.8 x 1.5 mA/MHz x 4 MHz + 0.15 x 0.8 mA/MHz x 4 MHz + 14 mA) = 22.5 µA + 0.1 x (4.8 + 0. 22.5 µA + 0.1 x 19. 22.5 µA + 1.928 mA = 1.95 mA PSD834F2V (ac (dc 67/95 ...
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... PSD834F2V MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 37 ...
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... Parameter Parameter Figure 33. AC Measurement Load Circuit 1.5V Device Under Test AI03103b Test Condition OUT ) PSD834F2V Min. Max. Unit 3.0 3.6 V –40 85 ° °C Min. Max. Unit 30 pF 2.01 V 195 ...
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... PSD834F2V Table 41. AC Symbols for PLD Timing Signal Letters A Address Input C CEout Output D Input Data E E Input G Internal WDOG_ON signal I Interrupt Input L ALE Input N Reset Input or Output P Port Signal Output Q Output Data R WR, UDS, LDS, DS, IORD, PSEN Inputs S Chip Select Input ...
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... 0.45 < V < PLD_TURBO = Off MHz (Note ) PLD_TURBO = On MHz During Flash memory WRITE/Erase Only Read Only MHz MHz is valid at or below 0.2V –0.1. V IL1 CC IH1 PSD834F2V Min. Typ. Max. 0. –0.5 0.8 0. –0.5 0.2V CC 0.3 1.5 2.2 0.01 ...
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... PSD834F2V Figure 35. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Table 43. CPLD Combinatorial Timing Symbol Parameter CPLD Input Pin/ t Feedback to CPLD PD Combinatorial Output CPLD Input to CPLD t EA Output Enable CPLD Input to CPLD t ER Output Disable CPLD Register Clear t or ARP Preset Delay ...
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... CLCL -10 -15 Conditions Min Max Min Max Min Max 1/( 22 1/(t +t –10) 28 1/( 40 Clock Input 15 15 Clock Input 10 15 Clock Input PSD834F2V AI02860 -20 PT Turbo Aloc Off 18.8 15.8 23.2 18.8 33.3 31 Slew Unit 1 rate MHz MHz MHz – 73/95 ...
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... PSD834F2V Figure 37. Asynchronous Reset / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 38. Asynchronous Clock Mode Timing (product term clock) CLOCK INPUT REGISTERED OUTPUT 74/95 tARPW tARP tCHA tCLA tSA tHA tCOA AI02864 AI02859 ...
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... Any macrocell ARD Delay Minimum Clock t MINA Period -10 -15 Min Max Min +t ) 21.7 SA COA +t –10) 27.8 COA +t ) 33.3 CHA CLA 1 CNTA PSD834F2V -20 PT Turbo Aloc Off Max Min Max 19.2 16.9 23.8 20 Slew Unit Rate MHz MHz MHz – 6 ...
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... PSD834F2V Figure 39. Input Macrocell Timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 46. Input Macrocell Timing Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t NIB Input Low Time INL NIB Input to Combinatorial t INO Delay Note: 1 ...
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... AVPV Note and t are not required for 80C251 in Page Mode or 80C51XA in Burst Mode. AVLX LXAX 1 t AVLX t LXAX t LVLX ADDRESS VALID t AVQV ADDRESS VALID t SLQV t RLQV t RLRH t THEH ADDRESS OUT PSD834F2V DATA VALID DATA VALID t RHQX tRHQZ t EHEL t ELTL AI02895 77/95 ...
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... PSD834F2V Table 47. READ Timing Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD to Data Valid 8-bit Bus t RLQV RD or PSEN to Data Valid 8-bit Bus, ...
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... BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t THEH t AVPV ADDRESS OUT PSD834F2V DATA VALID DATA VALID t DVWH t WHDX t WHAX t EHEL t ELTL t WLMV t WHPV STANDARD MCU I/O OUT AI02896 79/95 ...
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... PSD834F2V Table 48. WRITE Timing Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to Leading Edge of WR SLWL t WR Data Setup Time DVWH t WR Data Hold Time WHDX t WR Pulse Width ...
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... Sector Erase Time-Out WHWLO t DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling) Q7VQV Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Parameter (pre-programmed) 2 PSD834F2V Min. Typ. Max. 8 2.2 ...
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... PSD834F2V Figure 42. Peripheral I/O READ Timing ALE/ BUS CSI RD Table 50. Port A Peripheral Data Mode READ Timing Symbol Parameter t Address Valid to Data Valid AVQV–PA t CSI Valid to Data Valid SLQV– Data Valid t RLQV– Data Valid 8031 Mode t Data In to Data Out Valid DVQV– ...
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... Any input used to select Port A Data Peripheral mode. 4. Data is already stable on Port A. 5. Data stable on ADIO pins to data on Port A. ADDRESS tWLQV (PA) Conditions 2 (Note ) 5 (Note ) 2 (Note ) PSD834F2V DATA OUT tWHQZ (PA) tDVQV (PA) PORT A DATA OUT AI02898 -10 -15 -20 Min Max Min Max Min Max ...
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... PSD834F2V Figure 44. Reset (RESET) Timing V (min NLNH-PO Power-On Reset RESET Table 52. Reset (Reset) Timing Symbol Parameter t RESET Active Low Time NLNH t Power On Reset Active Low Time NLNH– Warm Reset NLNH–A t RESET High to Operational Device OPR Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. ...
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... Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For Program or Erase PLD only. ISCCH t ISCCL t t ISCPSU ISCPH Conditions 1 (Note ) 1 (Note ) 1 (Note ) 2 (Note ) 2 (Note ) 2 (Note ) PSD834F2V t ISCPZV t ISCPCO t ISCPVZ AI02865 -10 -15 -20 Min Max Min Max Min Max 240 240 240 240 ...
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... PSD834F2V PACKAGE MECHANICAL In order to meet environmental requirements, ST offers these devices in different grades of ECO- PACK® packages, depending on their level of en- vironmental compliance. Figure 46. PQFP52 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 GND 9 PC3 10 PC2 11 PC1 12 PC0 13 86/95 ® ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECO- ® ...
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... Figure 47. PLCC52 Connections 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 GND 17 PC3 18 PC2 19 PC1 20 PC0 PSD834F2V AD15 46 AD14 45 44 AD13 AD12 43 AD11 42 41 AD10 AD9 40 AD8 AD7 37 AD6 36 AD5 35 AD4 34 AI02857 87/95 ...
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... PSD834F2V Figure 48. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing QFP-A Note: Drawing is not to scale. 88/ ...
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... PSD834F2V inches Min. Max. 0.093 0.010 0.077 0.083 0.009 0.015 0.004 0.009 0.518 0.522 0.392 0.396 – – 0.518 0.522 0.392 0.396 – ...
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... PSD834F2V Figure 49. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing PLCC-B Note: Drawing is not to scale. Table 56. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions Symbol Typ 1. 90/ D2/ Min. Max. 4.19 4.57 2.54 2.79 – 0.91 0.33 0.53 ...
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... I = – °C (Industrial) Option T = Tape & Reel Packing Note: 1. The 5V±10% devices are not covered by this data sheet, but by the PSD834F2 data sheet. For a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact your nearest ST Sales Office. ...
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... PSD834F2V APPENDIX A. PQFQ52 PIN ASSIGNMENTS Table 58. PQFP52 Connections (Figure 46) Pin Number Pin Assignments 92/95 Pin Number PD2 PD1 PD0 PC7 PC6 PC5 PC4 V CC GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 GND PA2 PA1 PA0 AD0 AD1 AD2 ...
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... Pin Number GND PB5 PB4 PB3 PB2 PB1 PB0 PD2 PD1 PD0 PC7 PC6 PC5 PC4 V CC GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 GND PSD834F2V Pin Assignments 27 PA2 28 PA1 29 PA0 30 AD0 31 AD1 32 AD2 33 AD3 34 AD4 35 AD5 36 AD6 37 AD7 ...
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... PSD834F2V REVISION HISTORY Table 60. Document Revision History Date Version 15-Feb-2002 1.0 Document written 18-Nov-03 2.0 Reformatted; correct package references (Figure 1) Updated datasheet status to “not for new design”. Backup battery feature removed: updated FEATURES SUMMARY, Table 4 (pins PC2 and PC4 configurations ), KEY FEATURES, Memory section, SRAM section, Port C – ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com PSD834F2V 95/95 ...