MT48H8M32LFB5-75:H TR Micron Technology Inc, MT48H8M32LFB5-75:H TR Datasheet - Page 21

• Manufacturer Part Number: MT48H8M32LFB5-75:H TR
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BURST TERMINATE
AUTO REFRESH
SELF REFRESH
Auto Precharge
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
The BURST TERMINATE command is used to truncate either fixed-length or continuous
page bursts. The most recently registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in “Operations” on page 23.
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAM. This command is non persis-
tent, so it must be issued each time a refresh is required. All active banks must be PRE-
CHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum
CHARGE command, as shown in “Operations” on page 23.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 256Mb SDRAM requires
8192 AUTO REFRESH cycles every 64ms (
command every 7.8125µs will meet the refresh requirement and ensure that each row is
refreshed. Alternatively, 8192 AUTO REFRESH commands can be issued in a burst at the
minimum cycle rate (
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command, except CKE is disabled (LOW). Once the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking, caus-
ing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to
indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock ball) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
7.8125µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Auto precharge is a feature which performs the same individual-bank precharge func-
tion described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE com-
mand. A precharge of the bank/row that is addressed with the READ or WRITE com-
mand is automatically performed upon completion of the READ or WRITE burst, except
in the continuous page burst mode, where auto precharge does not apply. Auto pre-
charge is non persistent in that it is either enabled or disabled for each individual READ
or WRITE command.
t
RFC), once every 64ms.
21
t
RAS and may remain in self refresh mode for an
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
REF). Providing a distributed AUTO REFRESH
256Mb: x16, x32 Mobile SDRAM
t
RP has been met after the PRE-
t
XSR because time is
©2006 Micron Technology, Inc. All rights reserved.
Commands