MT48H8M32LFB5-75:H TR Micron Technology Inc, MT48H8M32LFB5-75:H TR Datasheet - Page 19

• Manufacturer Part Number: MT48H8M32LFB5-75:H TR
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
Table 5:
COMMAND INHIBIT
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or deep power-down
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Truth Table – Commands and DQM Operation
Notes 1 and 2 apply to all commands
Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.
Table 5 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional truth tables appear following “Opera-
tions” on page 23. These tables provide current state/next state information.
10. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
11. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
12. BA[1:0] select either the standard mode register or the extended mode register (BA0 = 0,
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
2. All states and sequences not shown are reserved and/or illegal.
3. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command
4. DESELECT and NOP are functionally interchangeable.
5. BA[1:0] provide bank address and A[12:0] provide row address.
6. BA[1:0] provide bank address; A[9:0] provide column address; A10 HIGH enables the auto
7. Applies only to read bursts with auto precharge disabled; this command is undefined (and
8. This command is a BURST TERMINATE if CKE is HIGH, deep power-down if CKE is LOW.
9. A10 LOW: BA[1:0] determine which bank is precharged. A10 HIGH: all banks are pre-
could coincide with data on the bus. However, the DQs column reads a don’t care state to
illustrate that the BURST TERMINATE command can occur when there is no data present.
precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
charged and BA[1:0] are “Don’t Care.”
except for CKE.
BA1 = 0 select the standard mode register; BA0 = 0, BA1 = 1 select extended mode register;
other combinations of BA[1:0] are reserved.) A[12:0] provide the op-code to be written to
the selected mode register.
CS#
H
X
X
19
L
L
L
L
L
L
L
L
RAS# CAS# WE#
H
H
H
H
X
X
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
X
X
L
L
L
L
256Mb: x16, x32 Mobile SDRAM
X
H
H
H
H
X
X
L
L
L
L
DQM
L/H
L/H
X
X
X
X
X
X
X
H
L
Bank/Row
©2006 Micron Technology, Inc. All rights reserved.
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
X
X
High-Z
Active
Commands
Valid
DQs
X
X
X
X
X
X
X
X
Notes
3, 7, 8
10, 11
12
4
4
5
6
6
9