MT48LC8M16A2P-75:G Micron Technology Inc, MT48LC8M16A2P-75:G Datasheet - Page 34

IC SDRAM 128MBIT 133MHZ 54TSOP

MT48LC8M16A2P-75:G

Manufacturer Part Number
MT48LC8M16A2P-75:G
Description
IC SDRAM 128MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr

Specifications of MT48LC8M16A2P-75:G

Memory Type
SDRAM
Format - Memory
RAM
Memory Size
128M (8Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Memory Configuration
16M X 8
Access Time
5.4ns
Page Size
128Mbit
Memory Case Style
TSOP
No. Of Pins
54
Operating Temperature Range
0°C To +70°C
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC8M16A2P-75:G
Manufacturer:
MICRON
Quantity:
8
Part Number:
MT48LC8M16A2P-75:G
Manufacturer:
MICRON
Quantity:
8 000
Part Number:
MT48LC8M16A2P-75:G
Manufacturer:
MICRON
Quantity:
20 000
Figure 27:
Figure 28:
Concurrent Auto Precharge
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. M 10/07 EN
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Note:
COMMAND
COMMAND
An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
INTERNAL
INTERNAL
ADDRESS
ADDRESS
CLOCK
CLOCK
For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
CLK
CKE
CLK
CKE
D
DQ
IN
T0
NOP
BANK,
READ
COL n
T0
WRITE
BANK,
COL n
T1
T1
D
NOP
n
IN
TRANSITIONING DATA
T2
T2
NOP
34
D
OUT
n
TRANSITIONING DATA
T3
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n + 1
D
OUT
NOP
n + 1
T4
T4
D
NOP
IN
DON’T CARE
T5
T5
n + 2
NOP
D
NOP
IN
n + 2
D
OUT
64Mb: x4, x8, x16 SDRAM
DON’T CARE
T6
NOP
D
n + 3
OUT
©2000 Micron Technology, Inc. All rights reserved.
Commands

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