C8051F986-GUR Silicon Labs, C8051F986-GUR Datasheet - Page 238

• Manufacturer Part Number: C8051F986-GUR
• Description: 8-bit Microcontrollers - MCU 8kB 512B RAM 12b ADC
• Manufacturer: Silicon Labs

Specifications of C8051F986-GUR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F99x-C8051F98x
22.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 22.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “25. Timers” on page 276.
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 22.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 22.2.
Figure 22.4 shows the typical SCL generation described by Equation 22.2. Notice that T
twice as large as T
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 22.1.
238
Timer Source
Overflows
SCL
LOW
T
Equation 22.1. Minimum SCL High and Low Times
. The actual SCL output may vary due to other devices on the bus (SCL may be
Low
SMBCS1
T
Figure 22.4. Typical SMBus SCL Generation
Table 22.1. SMBus Clock Source Selection
HighMin
0
0
1
1
Equation 22.2. Typical SMBus Bit Rate
BitRate
SMBCS0
=
T
High
T
0
1
0
1
LowMin
=
f
--------------------------------------------- -
ClockSourceOverflow
Rev. 1.1
Timer 2 High Byte Overflow
=
Timer 2 Low Byte Overflow
SMBus Clock Source
--------------------------------------------- -
f
ClockSourceOverflow
Timer 0 Overflow
Timer 1 Overflow
3
1
SCL High Timeout
HIGH
is typically