C8051F986-GUR Silicon Labs, C8051F986-GUR Datasheet - Page 143

• Manufacturer Part Number: C8051F986-GUR
• Description: 8-bit Microcontrollers - MCU 8kB 512B RAM 12b ADC
• Manufacturer: Silicon Labs

Specifications of C8051F986-GUR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

SFR Definition 13.3. EIE1: Extended Interrupt Enable 1
SFR Page = All; SFR Address = 0xE6
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
EWADC0 Enable Window Comparison ADC0 Interrupt.
ERTC0A Enable SmaRTClock Alarm Interrupts.
Unused
ESMB0
EPCA0
EADC0
Name
ECP0
ET3
R/W
ET3
7
0
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
Read = 0b. Write = Don’t care.
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by a SmaRTClock Alarm.
Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
R
6
0
ECP0
R/W
5
0
EPCA0
R/W
Rev. 1.1
4
0
C8051F99x-C8051F98x
Function
EADC0
R/W
3
0
EWADC0
R/W
2
0
ERTC0A
R/W
1
0
ESMB0
R/W
0
0
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