C8051F986-GUR Silicon Labs, C8051F986-GUR Datasheet - Page 181

• Manufacturer Part Number: C8051F986-GUR
• Description: 8-bit Microcontrollers - MCU 8kB 512B RAM 12b ADC
• Manufacturer: Silicon Labs

Specifications of C8051F986-GUR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

is enabled and selected as a reset source. The enable state of the V
a reset source is only altered by power-on and power-fail resets. For example, if the V
de-selected as a reset source and disabled by software, then a software reset is performed, the V
supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in Sleep Mode prior to a power-fail reset occurring. When the device is in Sleep
Mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as
V
while the user is replacing the battery. Upon waking from Sleep mode, the enable and reset source select
state of the V
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the V
interrupt. See Section “13. Interrupt Handler” on page 137 for more details.
Important Note: To protect the integrity of Flash contents, the V
and selected as a reset source if software contains routines which erase or write Flash memory. If
the V
Error device reset.
Important Notes:



1. Enable the V
2. Wait for the V
3. Select the V
DD
The Power-on Reset (POR) delay is not incurred after a V
“4. Electrical Characteristics” on page 46 for complete electrical characteristics of the V
Software should take care not to inadvertently disable the V
to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should
explicitly set PORSF to 1 to keep the V
The V
supply monitor as a reset source before it has stabilized may generate a system reset. In systems
where this reset would be undesirable, a delay should be introduced between enabling the V
monitor and selecting it as a reset source. See Section “4. Electrical Characteristics” on page 46 for
minimum V
software contains routines that erase or write Flash memory. The procedure for enabling the V
supply monitor and selecting it as a reset source is shown below:
does not fall below V
DD
DD
supply monitor is not enabled, any erase or write performed on Flash memory will cause a Flash
DD
supply falls below the V
supply monitor must be enabled before selecting it as a reset source. Selecting the V
DD
DD
DD
DD
supply monitor are restored to the value last set by the user.
DD
Supply Monitor turn-on time. No delay should be introduced in systems where
Supply Monitor as a reset source (PORSF bit in RSTSRC = 1).
Supply Monitor (VDMEN bit in VDM0CN = 1).
Supply Monitor to stabilize (optional).
POR
. A large capacitor can be used to hold the power supply voltage above V
WARN
threshold. The VDDOK bit can be configured to generate an
DD
Monitor enabled as a reset source.
Rev. 1.1
C8051F99x-C8051F98x
DD
DD
supply monitor reset. See Section
Monitor as a reset source when writing
DD
DD
supply monitor must be enabled
supply monitor and its selection as
DD
supply monitor is
DD
monitor.
DD
DD
supply
POR
DD
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DD