MAX9273GTL+ Maxim Integrated, MAX9273GTL+ Datasheet - Page 34

• Manufacturer Part Number: MAX9273GTL+
• Description: Serializers & Deserializers - Serdes 1.5Gbps 22-bit Coax/STP serializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9273GTL+

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CMOS/LVCMOS
• Output Type: CML
• Number Of Inputs: 22
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-40 EP
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

serializer and deserializer have unequal DBL settings
and HVEN = 0, then HS/VS inversion should only be used
on the side that has DBL = 1. HS/VS encoding sends
packets when HSYNC or VSYNC is low, use HS/VS inver-
sion register bits if the input HSYNC and VSYNC signals
use an active-low convention to send data packets dur-
ing the inactive pixel clock periods.
The driver output is programmable for two types of cable:
100I twisted pair and 50I coax (contact the factory for
serializers with 75I cable drive).
In coax mode, OUT+ and OUT- are active. This enables
use as a 1:2 splitter
OUT+ to IN+ of the deserializer. Connect OUT- to IN- of
the second deserializer. Control-channel data is broad-
cast from the serializer to both deserializers and their
Figure 31. 2:1 Coax-Mode Splitter Connection Diagram
Table 9. Configuration Input Map
Maxim Integrated
CONF1
High
High
High
Low
Low
Low
Mid
Mid
Mid
MAX9273
OUT+
OUT-
CONF0
High
High
High
Low
Low
Low
Mid
Mid
Mid
(Figure
31). In coax mode, connect
(OUT+/OUT- OUTPUT TYPE)
Coax-Mode Splitter
22-Bit GMSL Serializer with Coax or
Serial Output
IN+
IN-
IN+
IN-
Do not use
1 (coax)
1 (coax)
1 (coax)
1 (coax)
DESERIALIZER
DESERIALIZER
0 (STP)
0 (STP)
0 (STP)
0 (STP)
CxTP
GMSL
GMSL
attached peripherals. Assign a unique device address to
send control data to one deserializer. Leave all unused
IN_ pins unconnected, or connect them to ground
through 50I and a capacitor for increased power-supply
rejection. If OUT- is not used, connect OUT- to AVDD
through a 50I resistor
at the serializer, and at each deserializer, only one FC
can communicate at a time. Disable one splitter control-
channel link to prevent contention. Use the DIS_REV_P or
DIS_REV_N register bits to disable a control-channel link.
CONF1 and CONF0 determine the power-up values of the
serial output type, the input data latch, and the control-
channel interface type
be changed after power-up by writing to the appropriate
register bits
Figure 32. Coax-Mode Connection Diagram
(PCLKIN LATCH EDGE)
Do not use
1 (falling)
1 (falling)
1 (falling)
1 (falling)
MAX9273
0 (rising)
0 (rising)
0 (rising)
0 (rising)
Configuration Inputs (CONF1, CONF0)
ES
OUT+
OUT-
STP Cable Drive
(Figure
AVDD
(Table
(CONTROL-CHANNEL TYPE)
50I
0 (UART-to-I
0 (UART-to-I
0 (UART-to-I
0 (UART-to-I
32). When there are FCs
9). These functions can
1 (I
1 (I
1 (I
1 (I
MAX9273
Do not use
I2CSEL
2
2
2
2
C-to-I
C-to-I
C-to-I
C-to-I
IN+
IN-
DESERIALIZER
2
2
2
2
C/UART)
C/UART)
C/UART)
C/UART)
2
2
2
2
GMSL
C)
C)
C)
C)
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