MAX9273GTL+ Maxim Integrated, MAX9273GTL+ Datasheet - Page 12

• Manufacturer Part Number: MAX9273GTL+
• Description: Serializers & Deserializers - Serdes 1.5Gbps 22-bit Coax/STP serializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9273GTL+

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CMOS/LVCMOS
• Output Type: CML
• Number Of Inputs: 22
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-40 EP
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Maxim Integrated
15, 39
PIN
18
19
20
21
22
23
24
25
26
28
29
30
31
35
—
RX/SDA
PCLKIN
CONF0
CONF1
TX/SCL
AUTOS
IOVDD
NAME
GPIO1
PWDN
DVDD
OUT+
OUT-
GPO
DRS
MS
EP
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1FF
and 0.001FF capacitors as close as possible to the device with the smallest value capacitor
closest to IOVDD.
General-Purpose Output. GPO follows the GMSL deserializer GPI (or INT) input. GPO = low
upon power-up and when PWDN = low.
Open-Drain, General-Purpose Input/Output with Internal 60kI Pullup to IOVDD
Mode-Select Input with Internal Pulldown to EP. Set MS = low to select base mode.
Set MS = high to select bypass mode.
Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter
power-down mode to reduce power consumption.
Data-Rate Select Input with Internal Pulldown to EP (Table 15).
Configuration 0. Three-level configuration input (Table 9).
Configuration 1. Three-level configuration input (Table 9).
Inverting Coax/Twisted-Pair Serial Output
Noninverting Coax/Twisted-Pair Serial Output
UART Receive or I
mode, RX/SDA is the Rx input of the serializer’s UART. In the I
SDA input/output of the serializer’s I
requires a pullup resistor.
UART Transmit or I
mode, TX/SCL is the Tx output of the serializer’s UART. In the I
input/output of the serializer’s I
a pullup resistor.
Autostart Input with Internal Pulldown to EP. AUTOS = low enables serialization upon power-
up and automatic frequency range selection of PCLKIN. AUTOS = high puts the part in sleep
mode upon power-up.
Parallel Clock Input with Internal Pulldown to EP. Latches parallel data inputs and provides
the PLL reference clock.
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1FF and 0.001FF capacitors as close
as possible to the device with the smaller value capacitor closest to DVDD.
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB
ground plane through an array of vias for proper thermal and electrical performance.
22-Bit GMSL Serializer with Coax or
2
2
C Serial-Data Input/Output with Internal 30kI Pullup to IOVDD. In UART
C Serial-Clock Input/Output with Internal 30kI Pullup to IOVDD. In UART
2
C master/slave. TX/SCL has an open-drain driver and requires
2
C master/slave. RX/SDA has an open-drain driver and
FUNCTION
Pin Description (continued)
STP Cable Drive
2
2
C mode, RX/SDA is the
C mode, TX/SCL is the SCL
MAX9273
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