MAX9273GTL+ Maxim Integrated, MAX9273GTL+ Datasheet - Page 24

• Manufacturer Part Number: MAX9273GTL+
• Description: Serializers & Deserializers - Serdes 1.5Gbps 22-bit Coax/STP serializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9273GTL+

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CMOS/LVCMOS
• Output Type: CML
• Number Of Inputs: 22
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-40 EP
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Figure 17. Serial-Data Format
Table 3. Data-Rate Selection Table
The deserializer uses differential line coding to send
signals over the reverse channel to the serializer. The
bit rate of the control channel is 9.6kbps to 1Mbps in
both directions. The serializer/deserializer automatically
detect the control-channel bit rate in base mode. Packet
bit-rate changes can be made in steps of up to 3.5
times higher or lower than the previous bit rate. See the
Changing the Clock Frequency
tion on changing the control-channel bit rate.
Figure 19
Figure 21
and the ACK byte (0xC3). The FC and the connected
slave chip generate the SYNC byte and ACK byte,
respectively. Events such as device wake-up and GPI
generate transitions on the control channel that can be
ignored by the FC. Data written to the serializer/deserial-
Maxim Integrated
D0
NOTE: SERIAL DATA SHOWN BEFORE SCRAMBLING AND 8b/10b ENCODING
DRS SETTING
shows the UART data format.
detail the formats of the SYNC byte (0x79)
D1
0
0
0
0
1
1
1
1
VIDEO AND ERROR-
CORRECTION DATA
24 BITS
D21
section for more informa-
1 (double input)
DBL SETTING
0 (single input)
CHANNEL BIT
22-Bit GMSL Serializer with Coax or
CONTROL-
FORWARD
FCC
0
1
0
0
1
1
CHECK BIT
Figure 20
PACKET
PARITY
PCB
and
D0
BWS SETTING
0 (24-bit mode)
1 (32-bit mode)
izer registers do not take effect until after the acknowl-
edge byte is sent. This allows the FC to verify that write
commands are received without error, even if the result
of the write command directly affects the serial link. The
slave uses the SYNC byte to synchronize with the host
UART’s data rate. If the GPI or MS/HVEN inputs of the
deserializer toggle while there is control-channel com-
munication, or if a line fault occurs, the control-channel
communication is corrupted. In the event of a missed
or delayed acknowledge (~1ms due to control-channel
timeout), the FC should assume there was an error in the
packet when the slave device received it, or that an error
occurred during the response from the slave device. In
base mode, the FC must keep the UART Tx/Rx lines high
for 16 bit times before starting to send a new packet.
D1
0
1
0
1
0
1
VIDEO AND ERROR-
CORRECTION DATA
STP Cable Drive
32 BITS
PCLKIN RANGE (MHz)
8.33 to 16.66
6.25 to 12.5
16.66 to 50
33.3 to 100
Do not use
Do not use
12.5 to 35
25 to 75
MAX9273
D29
CHANNEL BIT
CONTROL-
FORWARD
FCC
CHECK BIT
PACKET
PARITY
PCB
24