MAX9273GTL+ Maxim Integrated, MAX9273GTL+ Datasheet - Page 33

• Manufacturer Part Number: MAX9273GTL+
• Description: Serializers & Deserializers - Serdes 1.5Gbps 22-bit Coax/STP serializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9273GTL+

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CMOS/LVCMOS
• Output Type: CML
• Number Of Inputs: 22
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-40 EP
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Table 8. Modulation Coefficients and
Maximum SDIV Settings
In default mode (additional error detection and correction
disabled), data encoding/decoding is the same as in pre-
vious GMSL serializers/deserializers (parity only). At the
serializer, the parallel input word is scrambled and a par-
ity bit added. The scrambled word is divided into 3 or 4
bytes (depending on the BWS setting), 8b/10b encoded,
and then transmitted serially. At the deserializer, the same
operations are performed in reverse order. The parity bit
is used by the deserializer to find the word boundary and
for error detection. Errors are counted in an error counter
register and an error pin indicates errors.
The serializer can use of of two additional error-detection/
correction methods (selectable by register setting):
1) 6-bit cyclic redundancy check
2) 6-bit hamming code with 16-word interleaving
When CRC is enabled, the serializer adds 6 bits of CRC to
the input data. This reduces the available bits in the input
data word by 6, compared to the non-CRC case (see
Table 2
input data instead of 22 bits when BWS = 0, and 24 bits
instead of 30 bits when BWS = 1.
The CRC generator polynomial is x
the ITU-T G704 telecommunication standard).
Maxim Integrated
BWS
Additional Error Detection and Correction
1
0
for details). For example, 16 bits are available for
SETTING (%)
SPECTRUM
SPREAD-
0.5
1.5
0.5
1.5
1
3
4
2
1
3
4
2
Cyclic Redundancy Check (CRC)
MODULATION
COEFFICIENT
(dec)
104
104
152
152
204
204
112
112
152
152
80
80
6
22-Bit GMSL Serializer with Coax or
+ x + 1 (as used in
SDIV UPPER
LIMIT (dec)
40
63
27
54
15
30
52
63
37
63
21
42
The parity bit is still added when CRC is enabled,
because it is used for word-boundary detection. When
CRC is enabled, each data word is scrambled and then
the 6-bit CRC and 1-bit parity are added before the
8b/10b encoding.
At the deserializer, the CRC code is recalculated. If the
recalculated CRC code does not match the received CRC
code, an error is flagged. This CRC error is reported to the
error counter.
Hamming code is a simple and effective error-correction
code to detect and/or correct errors. The MAX9273 seri-
alizer (when used with the MAX9272 GMSL deserializer)
uses single-error correction/double-error detection per
pixel hamming-code scheme.
The serializer uses data interleaving for burst-error toler-
ance. Burst errors up to 11 consecutive bits on the serial
link are corrected, and burst errors up to 31 consecutive
bits are detected.
Hamming code adds overhead similar to CRC. See
for details regarding the available input word size.
HS/VS encoding by a GMSL serializer allows horizontal
and vertical synchronization signals to be transmitted
while conserving pixel data bandwidth. With HS/VS
encoding enabled, 10-bit pixel data with a clock up to
100MHz can be transmitted using 1 pixel of data per HS/
VS transition, versus 8-bit data with a clock up to 100MHz
without HS/VS encoding. The deserializer performs HV
decoding, tracks the period of the HV signals, and uses
voting to filter HS/VS bit errors. When using HV encod-
ing, use a minimum low-pulse duration of two PCLKIN
cycles when DBL = 0 on the MAX9271/MAX9273. When
DBL = 1, use a minimum HS/VS low-pulse duration of
five PCLKIN cycles and a minimum high-pulse duration
of two PCLKIN cycles. When using hamming code and
HS/VS encoding, do not send more than two transitions
every 16 PCLKIN cycles.
When the serializer uses double-input mode (DBL = 1),
the active duration, plus the blanking duration of HS or
VS signals, should be an even number of PCLKIN cycles.
If HS/VS tracking is used without HV encoding, use DIN0
for HSYNC and DIN1 for VSYNC. In this case, if DBL
values on the serializer and the deserializer are different,
set the deserializer’s UNEQDBL register bit to 1. If the
HS/VS Encoding and/or Tracking
STP Cable Drive
MAX9273
Hamming Code
Table 2
33