QL4009-0PF100C ETC1 [List of Unclassifed Manufacturers], QL4009-0PF100C Datasheet - Page 4

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QL4009-0PF100C

Manufacturer Part Number
QL4009-0PF100C
Description
9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet

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QL4009 QuickRAM Data Sheet Rev B
www.quicklogic.com
AC Characteristics at V
a. These limits are derived from a representative selection of the slowest paths through the Quick-
t
t
t
t
t
t
t
t
t
t
PD
SU
H
CLK
CWHI
CWLO
SET
RESET
SW
RW
RAM logic cell including typical net delays. Worst case delay values for specific paths should be
determined from timing analysis of your particular design.
To calculate delays, multiply the appropriate K factor from
following numbers in the tables provided.
Symbol
Combinatorial Delay
Setup Time
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
CC
Figure 3: QuickRAM Logic Cell
Parameter
a
QS
A1
A2
A3
A4
A5
A6
QS
OP
B1
B2
C1
C2
MP
MS
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
QC
QR
= 3.3 V, T
Table 1: Logic Cell
a
A
= 25 C (K = 1.00)
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
1
Propagation Delays (ns)
AZ
OZ
QZ
NZ
FZ
1.7
1.7
0.0
1.0
1.2
1.2
1.3
1.1
1.9
1.8
2
Fanout (5)
Table 10: Operating Range
1.9
1.7
0.0
1.2
1.2
1.2
1.5
1.3
1.9
1.8
3
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
4
© 2002 QuickLogic Corporation
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
5
by the

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