QL4009-0PF100C ETC1 [List of Unclassifed Manufacturers], QL4009-0PF100C Datasheet
QL4009-0PF100C
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QL4009-0PF100C Summary of contents
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... QL4009 QuickRAM Data Sheet • • • • • • 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights High Performance & High Density 9,000 Usable PLD Gates with 82 I/Os • 300 MHz 16-bit Counters, 400 MHz • ...
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... QL4009 QuickRAM Data Sheet Rev B Architecture Overview The QuickRAM combination with Dual-Port SRAM modules. The QL4009 is a 9,000 usable PLD gate member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35 m four-layer metal process using QuickLogic's patented ViaLink unique combination of high performance, high density, low cost, and extreme ease-of-use. ...
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... Input + logic cell + output total delays under 6 ns • Data path speeds over 400 MHz • Counter speeds over 300 MHz • FIFO speeds over 160+ MHz • © 2002 QuickLogic Corporation QL4009 QuickRAM Data Sheet Rev B www.quicklogic.com • • • 3 • • • ...
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... QL4009 QuickRAM Data Sheet Rev B AC Characteristics calculate delays, multiply the appropriate K factor from following numbers in the tables provided. Symbol CLK t CWHI t CWLO t SET t RESET These limits are derived from a representative selection of the slowest paths through the Quick- RAM logic cell including typical net delays ...
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... Operating Range. © 2002 QuickLogic Corporation [8:0] WA [17:0] RCLK WCLK [1:0] MODE ASYNCRD Figure 4: QuickRAM Module Table 2: RAM Cell Synchronous Write Timing Parameter 1.0 0.0 1.0 0.0 1.0 0.0 a 5.0 Table 3: RAM Cell Synchronous Read Timing Parameter 1.0 0.0 1.0 0.0 a 4.0 QL4009 QuickRAM Data Sheet Rev B RE [8:0] [17:0] RD Propagation Delays (ns) Fanout 1.0 1.0 1.0 1.0 0.0 0.0 0.0 0.0 1.0 1.0 1.0 1.0 0.0 0.0 0.0 0.0 1.0 1.0 1.0 1.0 ...
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... QL4009 QuickRAM Data Sheet Rev B Symbol RPDRD a. Stated timing for worst case Propagation Delay over process variation Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. Symbol t High Drive Input Delay IN t High Drive Input, Inverting Delay ...
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... The following loads are used for t © 2002 QuickLogic Corporation Table 7: I/O Cell Input Delays Parameter 1.3 3.1 0.0 0.7 0.6 2.3 0.0 Table 8: I/O Cell Output Delays Propagation Delays (ns) Parameter Output Load Capacitance (pF) 3 2.1 2.2 1.2 1.6 a 2.0 a 1.2 PXZ tPHZ 5 pF QL4009 QuickRAM Data Sheet Rev B Propagation Delays (ns) a Fanout 1.6 1.8 2.1 3.1 3.6 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 1.0 1.2 1 ...
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... QL4009 QuickRAM Data Sheet Rev B DC Characteristics The DC specifications are provided in the tables below. Parameter V Voltage CC V Voltage CCIO Input Voltage Latch-up Immunity Symbol V Supply Voltage CC V I/O Input Tolerance Voltage CCIO T Ambient Temperature A T Case Temperature C K Delay Factor • • ...
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... 1 GND I CCIO GND I CCIO GND GND I IO CCIO CCIO QL4009 QuickRAM Data Sheet Rev B Min Max Units 0. CCIO -0.5 0. 2 0. -10 10 µA -10 10 µ -15 -180 ...
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... QL4009 QuickRAM Data Sheet Rev B Kv and Kt Graphs 1.1000 1.0800 1.0600 1.0400 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 • • • www.quicklogic.com 10 • • • Voltage Factor vs. Supply Voltage 3 3.1 3.2 3.3 Supply Voltage (V) Figure 5: Voltage Factor vs. Supply Voltage Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 ...
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... Time Figure 7: Power-up Requirements above) when ramping the device. CC earlier than 400 µs can cause the device to behave improperly. and Figure 8: Internal Diode Between V QL4009 QuickRAM Data Sheet Rev 500 mV. Deviation from CCIO CC MAX . Ramping shown in . ...
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... QL4009 QuickRAM Data Sheet Rev B JTAG TCK TMS TRSTB RDI Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149 ...
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... TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. © 2002 QuickLogic Corporation QL4009 QuickRAM Data Sheet Rev B The Extest instruction performs a PCB interconnect test. This test This instruction allows a device to remain in its The Bypass instruction allows data to skip a device's boundary • ...
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... QL4009 QuickRAM Data Sheet Rev B Pin Descriptions Pin Test Data In for JTAG /RAM init. TDI/RSI Serial Data In Active low Reset for JTAG /RAM TRSTB/RRO init. reset out TMS Test Mode Select for JTAG TCK Test Clock for JTAG Test data out for JTAG /RAM init. ...
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... I I/O TRSTB TDI I/O GCLK I/O ACLK/I QL4009 QuickRAM Data Sheet Rev GCLK GCLK/I VCC 52 ACLK/I 51 GCLK GND PLCC Function ...
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... QL4009 QuickRAM Data Sheet Rev B 84 PLCC Pinout Diagram 84 PLCC Pinout Table 84 PLCC Function 1 I/O 2 I CCIO 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 TDO 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 GND 20 I/O 21 GCLK/I • • • www.quicklogic.com 16 • • • ...
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... I I/O ACLK / GND 39 64 I/O 40 I/O 65 GCLK / I CCIO I/O 49 TRSTB TMS QL4009 QuickRAM Data Sheet Rev B Pin 76 Pin 51 100TQFP Function 76 I/O TCK 77 I/O STM 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I/O 82 I/O I/O 83 I/O I/O 84 GND I/O I/O 85 GND 86 I I GND 89 I I/O 90 ...
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... Verilog is a registered trademark of Cadence Design Systems, Inc. © 2002 QuickLogic Corporation Table 16: Revision History Date Comments 5/2000 First release. Added Kfactor, Power-up, JTAG and mechanical 5/2002 drawing information. Reformatted. QL4009 QuickRAM Data Sheet Rev B www.quicklogic.com • • • 18 • • • ...