QL4009-0PF100C ETC1 [List of Unclassifed Manufacturers], QL4009-0PF100C Datasheet - Page 12

• Manufacturer Part Number: QL4009-0PF100C
• Description: 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

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QL4009 QuickRAM Data Sheet Rev B
www.quicklogic.com
JTAG
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design
challenges, not the least of which concerns the accessibility of test points. The Joint Test
Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard
1149.1, the Standard Test Access Port and Boundary Scan Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the
boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port
(TAP) controller works in concert with the Instruction Register (IR); these allow users to run
three required tests, along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse
subsystem tests for fuller verification of higher level system elements.
TRSTB
TMS
TCK
RDI
TAp Controller
State Machine
(16 States)
Mux
Figure 9: JTAG Block Diagram
Instruction Decode
Register
Internal
User Defined Data Register
Control Logic
&
Boundary-Scan Register
(Data Register)
Instruction Register
I/O Registers
Register
Bypass
Mux
© 2002 QuickLogic Corporation
TDO