HS9-82C37ARH/SAMPLE HARRIS [Harris Corporation], HS9-82C37ARH/SAMPLE Datasheet - Page 24

• Manufacturer Part Number: HS9-82C37ARH/SAMPLE
• Description: Radiation Hardened CMOS High Performance Programmable DMA Controller
• Manufacturer: HARRIS [Harris Corporation]

Command Register - This 8-bit register controls the
operation of the HS-82C37ARH. It is programmed by the
microprocessor and is cleared by Reset or a Master Clear
instruction. The adjacent table lists the function of the
command bits. See Figure 10 for Read and Write addresses.
Command Register
7
6
Read Status Register
Write Command Register
Read Request Register
Write Request Register
Read Command Register
Write Single Mask Bit
Read Mode Register
Write Mode Register
Set Byte Pointer F/F
Clear Byte Pointer F/F
Read Temporary Register
Master Clear
Clear Mode Reg. Counter
Clear Mask Register
Read All Mask Bits
Write All Mask Bits
5
4
OPERATION
3
2
1
0
FIGURE 10. SOFTWARE COMMAND CODES AND REGISTER CODES
0
1
0
1
X
0
1
0
1
X
0
1
0
1
X
0
1
0
1
MEM-TO-MEM DISABLE
MEM-TO-MEM ENABLE
CH. 0 ADDR. HOLD DISABLE
CH. 0 ADDR. HOLD ENABLE
IF BIT 0 = 0
CONTROLLER ENABLE
CONTROLLER DISABLE
NORMAL TIMING
COMPRESSED TIMING
IF BIT 0 = 1
FIXED PRIORITY
ROTATING PRIORITY
LATE WRITE SELECTION
EXTENDED WRITE SEL.
IF BIT 3 = 1
DREQ SENSE ACTIVE HIGH
DREQ SENSE ACTIVE LOW
DACK SENSE ACTIVE LOW
DACK SENSE ACTIVE HIGH
BIT NUMBER
A3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
HS-82C37ARH
A2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
24
Status Register - The Status Register contains information
about the present status of the HS-82C37ARH and can be
read by the microprocessor. This information includes which
channels have reached a terminal count and which channels
have pending DMA requests. Bits 0-3 are set every time a
TC is reached by that channel or an external EOP is applied.
These bits are cleared upon Reset, Master Clear, and on
each Status Read. Bits 4-7 are set whenever their corre-
sponding channel is requesting service, regardless of the
mask bit state. If the mask bits are set, software can poll the
Status Register to determine which channels have DREQs,
and selectively clear a mask bit, thus allowing user defined
service priority. Status bits 4-7 are updated while the clock is
high, and latched on the falling edge. Status Bits 4-7 are
cleared upon Reset or Master Clear.
Status Register
Temporary Register - The Temporary Register is used to
hold data during Memory-to-Memory transfers. Following the
completion of the transfer, the last word moved can be read
by the microprocessor by accessing this register. The Tem-
porary Register always contains the last byte transferred in
the previous Memory-to-Memory operation, unless cleared
by a Reset or Master Clear.
7
A1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
6
5
4
3
A0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
2
1
0
IOR
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CHANNEL 0 HAS REACHED TC
CHANNEL 1 HAS REACHED TC
CHANNEL 2 HAS REACHED TC
CHANNEL 3 HAS REACHED TC
CHANNEL 0 REQUEST
CHANNEL 1 REQUEST
CHANNEL 2 REQUEST
CHANNEL 3 REQUEST
Spec Number
BIT NUMBER
IOW
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
518058