HS9-82C37ARH/SAMPLE HARRIS [Harris Corporation], HS9-82C37ARH/SAMPLE Datasheet

HS9-82C37ARH/SAMPLE

Manufacturer Part Number

HS9-82C37ARH/SAMPLE

Description

Radiation Hardened CMOS High Performance Programmable DMA Controller

Manufacturer

HARRIS [Harris Corporation]

Datasheet

1.HS9-82C37ARHSAMPLE.pdf (28 pages)

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August 1995

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.

Features

• Radiation Hardened

• Low Power Consumption

• Pin Compatible with NMOS 8237A and the Harris

• High Speed Data Transfers Up To 2.5 MBPS With 5MHz

• Four Independent Maskable Channels With Autoinitializa-

• Expandable to Any Number of Channels

• Memory-to-Memory Transfer Capability

• CMOS Compatible

• Hardened Field, Self-Aligned, Junction Isolated CMOS

• Single 5V Supply

• Military Temperature Range -55

Ordering Information

HS1-82C37ARH-Q

HS1-82C37ARH-8

HS1-82C37ARH-Sample

HS9-82C37ARH-Q

HS9-82C37ARH-8

HS9-82C37ARH/Sample

- Total Dose >10

- Transient Upset > 10

- Latch Up Free EPI-CMOS

- IDDSB = 50 A Maximum

- IDDOP = 4.0mA/MHz Maximum

82C37A

Clock

tion Capability

Process

Harris Corporation 1995

S E M I C O N D U C T O R

PART NUMBER

RAD (Si)

RAD (Si)/s

C to +125

TEMPERATURE RANGE

Performance Programmable DMA Controller

-55

HS-82C37ARH

C to +125

+25

Description

The Harris HS-82C37ARH is an enhanced, radiation

hardened CMOS version of the industry standard 8237A

Direct Memory Access (DMA) controller, fabricated using the

Harris hardened ﬁeld, self-aligned silicon gate CMOS

process. The HS-82C37ARH offers increased functionality,

improved performance, and dramatically reduced power

consumption for the radiation environment. The high speed,

radiation hardness, and industry standard conﬁguration of

the HS-82C37ARH make it compatible with radiation

hardened microprocessors such as the HS-80C85RH and

the HS-80C86RH.

The HS-82C37ARH can improve system performance by

allowing external devices to transfer data directly to or from

system memory. Memory-to-memory transfer capability is

also provided, along with a memory block initialization

feature. DMA requests may be generated by either

hardware or software, and each channel is independently

programmable with a variety of features for ﬂexible

operation.

Static CMOS circuit design insures low operating power and

allows gated clock operation for an even further reduction of

power. Multimode programmability allows the user to select

from three basic types of DMA services, and reconﬁguration

under program control is possible even with the clock to the

controller stopped. Each channel has a full 64K address and

word count range, and may be programmed to autoinitialize

these registers following DMA termination (end of process).

The Harris hardened ﬁeld CMOS process results in

performance equal to or greater than existing radiation resis-

tant products at a fraction of the power.

Radiation Hardened CMOS High

40 Lead SBDIP

42 Lead Ceramic Flatpack

PACKAGE

Spec Number

File Number

518058

3042.1

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HS9-82C37ARH/SAMPLE Summary of contents

Page 1

... Military Temperature Range -55 Ordering Information PART NUMBER HS1-82C37ARH-Q HS1-82C37ARH-8 HS1-82C37ARH-Sample HS9-82C37ARH-Q HS9-82C37ARH-8 HS9-82C37ARH/Sample CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. © Copyright Harris Corporation 1995 HS-82C37ARH Radiation Hardened CMOS High Performance Programmable DMA Controller ...

Page 2

Pinouts 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T40 TOP VIEW IOR 1 IOW 2 MEMR 3 MEMW READY 6 HLDA 7 ADSTB 8 AEN 9 HRQ CLK 12 RESET 13 DACK2 ...

Page 3

Pin Descriptions PIN SYMBOL NUMBER TYPE VDD 31 VDD: is the +5V power supply pin. A 0.1 F capacitor between pins 31 and 20 is recommended for de- coupling. GND 20 Ground CLK 12 I CLOCK INPUT: The Clock Input ...

Page 4

Pin Descriptions (Continued) PIN SYMBOL NUMBER TYPE A4-A7 37-40 O Address: The four most signiﬁcant address lines are three-state outputs and provide 4 bits of address. These lines are enabled only during the Active cycle. HRQ 10 O Hold Request: ...

Page 5

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS VCC = +5V 10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range. PARAMETER SYMBOL DMA (MASTER) MODE AEN HIGH from CLK LOW (S1) TCLAEH Delay Time DMA (MASTER) ...

Page 7

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) VCC = +5V 10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range. PARAMETER SYMBOL DMA (MASTER) MODE (Continued) DB Float to Active Delay from TCHDV CLK HIGH ...

Page 8

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) VCC = +5V 10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range. PARAMETER SYMBOL PERIPHERAL (SLAVE) MODE (Continued) ADR or CS Hold from IOR HIGH TIRHAX Data ...

Page 9

TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS o NOTE: See +25 C limits in Table 1 and Table 2 for Post RAD limits (Subgroups 1, 7 and 9). TABLE 5. BURN-IN DELTA PARAMETERS (+25 PARAMETER Standby Power Supply Current ...

Page 10

Harris Space Level Product Flow -Q Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Veriﬁcation (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Die Attach 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull ...

Page 11

Harris Space Level Product Flow -8 GAMMA Radiation Veriﬁcation (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Die Attach Periodic- Wire Bond Pull Monitor, Method 2011 Periodic- Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method ...

Page 12

Waveforms CS IOW A0-A3 DB0-DB7 NOTE: Host system must allow at least TCLCL as recovery time between successive write accesses CS A0-A3 TAVIRL IOR DB0-DB7 NOTE: Host system must allow at least TCLCL as recovery time between successive write accesses ...

Page 13

Waveforms (Continued CLK TDQVCL DREQ TCHRQV HRQ HLDA AEN TCLSH ADSTB TCHDV DB0-DB7 TCHAV A0-A7 DACK TCHRWV * READ * WRITE INT EOP EXT EOP * READ refers to both IOR and MEMR outputs. WRITE refers ...

Page 14

Waveforms (Continued) S0 S11 S12 CLK TCLSH ADSTB TCHAV TCHDZ TCHDV DB0 - DB7 A8 - A15 TCHRWL MEMR TCHRVW INT EOP VDD RESET IOR OR IOW HS-82C37ARH S13 S14 S21 TCLSH TCLSL TSLDZ TCHAV ADDRESS VALID ...

Page 15

Waveforms (Continued) CLK TCHAV TCHRWL * READ * WRITE READY * READ refers to both IOR and MEMR outputs. WRITE refers to both IOW and MEMW outputs HS-82C37ARH TCHAV VALID TCHRH TCHRWL TRLRH2 TCHWH ...

Page 16

Burn-In Circuits HS-82C37ARH 40 LEAD SBDIP STATIC CONFIGURATION NOTES: 1. VDD = +6.0V 5% Part is Static Sensitive ...

Page 17

Burn-In Circuits (Continued) HS-82C37ARH 42 LEAD CERAMIC FLATPACK ...

Page 18

Irradiation Circuit LOAD LOAD LOAD LOAD LOAD TOGGLE CLOCK RESET TOGGLE LOAD 2 LOAD 2 NOTES 47k 2. Pins with Load 10, 37-40 Pins with Load2: 14, 15, 21-30 Pins Brought Out: 12 ...

Page 19

Functional Description The HS-82C37ARH Direct Memory Access Controller is designed to improve the data transfer rate in systems which must transfer data from an I/O device to memory, or move a block of memory to an I/O device. It will ...

Page 20

Note that the data is transferred directly from the I/O device to memory (or vice versa) with IOR and MEMW (or MEMR and IOW) being active at the same time. The data is not read into or driven out of ...

Page 21

HS-80C86RH MICRO- 1ST LEVEL PROCESSOR HRQ DREQ HLDA DACK HS-82C37ARH DREQ DACK INITIAL DEVICE FIGURE 9. CASCADED HS-82C37ARHs When programming cascaded controllers, start with the ﬁrst level (closest to the microprocessor). After RESET, the DACK outputs are programmed to be ...

Page 22

Rotating Priority 1sr 2nd Service Service Highest 0 2 service 1 service 3 request 2 0 Lowest 3 1 With Rotating Priority in a single chip DMA system, any device requesting service is guaranteed to be recognized after no more ...

Page 23

Mask Register - Each channel has associated with it a mask bit which can be set to disable an incoming DREQ. Each mask bit is set when its associated channel produces an EOP if the channel is not programmed to ...

Page 24

Command Register - This 8-bit register controls the operation of the HS-82C37ARH programmed by the microprocessor and is cleared by Reset or a Master Clear instruction. The adjacent table lists the function of the command bits. See Figure ...

Page 25

Software Commands There are special software commands which can be exe- cuted by reading or writing to the HS-82C37ARH. These commands do not depend on the speciﬁc data pattern on the data bus, but are activated by the I/O operation ...

Page 26

Application Information Figure 12 shows an application for a DMA system utilizing the HS-82C37ARH DMA controller and the HS-80C86RH Microprocessor. In this application, the HS-82C37ARH DMA controller is used to improve system performance by allow- ing an I/O device to ...

Page 27

Metallization Topology DIE DIMENSIONS: 215 x 232 mils mil METALLIZATION: Type: Al/Si Å Å Thickness: 11k 2k GLASSIVATION: Å Å Thickness WORST CASE CURRENT DENSITY 7 A/cm Metallization Mask Layout HLDA ...

Page 28

Packaging LEAD FINISH BASE METAL (b) SECTION A-A NOTES: 1. Index area: A notch or a pin one identiﬁcation mark shall be locat- ed adjacent to pin one ...

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