HS9-82C37ARH/SAMPLE HARRIS [Harris Corporation], HS9-82C37ARH/SAMPLE Datasheet - Page 23

• Manufacturer Part Number: HS9-82C37ARH/SAMPLE
• Description: Radiation Hardened CMOS High Performance Programmable DMA Controller
• Manufacturer: HARRIS [Harris Corporation]

Mask Register - Each channel has associated with it a
mask bit which can be set to disable an incoming DREQ.
Each mask bit is set when its associated channel produces
an EOP if the channel is not programmed to Autoinitialize.
Each bit of the 4-bit Mask Register may also be set or
cleared separately or simultaneously under soft-ware con-
trol. The entire register is also set by a Reset or Master
Clear. This disables all hardware DMA requests until a clear
Mask Register instruction allows them to occur. The instruc-
tion to separately set or clear the mask bits is similar in form
to that used with the Request Register. Refer to the following
table and Figure 10 for details. When reading the Mask Reg-
ister, bits 4-7 will always read as logical ones, and bits 0-3
will display the mask bits of channel 0-3, respectively. The 4
bits of the Mask Register may be cleared simultaneously by
using the Clear Mask Register command (see software com-
mands section).
Mask Register
All four bits of the Mask Register may also be written with a
single command.
7
7
DON’T CARE,
WRITE ALL
DON’T CARE
6
ONES,
READ
6
5
5
4
4
3
3
2
2
1
1
0
0
00
01
10
11
0
1
0
1
0
1
0
1
0
1
SELECT CHANNEL 0 MASK BIT
SELECT CHANNEL 1 MASK BIT
SELECT CHANNEL 2 MASK BIT
SELECT CHANNEL 3 MASK BIT
CLEAR MASK BIT
SET MASK BIT
CLEAR CHANNEL 0 MASK BIT
SET CHANNEL 0 MASK BIT
CLEAR CHANNEL 1 MASK BIT
SET CHANNEL 1 MASK BIT
CLEAR CHANNEL 2 MASK BIT
SET CHANNEL 2 MASK BIT
CLEAR CHANNEL 3 MASK BIT
SET CHANNEL 3 MASK BIT
BIT NUMBER
BIT NUMBER
HS-82C37ARH
23
Mode Register - Each channel has a 6-bit Mode Register
associated with it. When the register is being written to by
the microprocessor in the Program Condition, bits 0 and 1
determine which channel Mode Register is to be written.
When the processor reads a Mode Register, bits 0 and 1 will
both be ones. See the adjacent table and Figure 10 for Mode
Register functions and addresses.
Mode Register
Request Register - The HS-82C37ARH can respond to
requests for DMA service which are initiated by software as
well as by a DREQ. Each channel has a request bit associ-
ated with it in the 4-bit Request Register. These are non-
maskable and subject to prioritization by the Priority Encoder
network. Each register bit is set or reset separately under
software control. The entire register is cleared by a Reset. To
set or reset a bit, the software loads the proper form of the
data word. See Figure 10 for register address coding, and
the following table for Request Register format. A software
request for DMA operation can be made in Block or Single
Modes. For Memory-to-Memory transfers, the software
request for channel 0 should be set. When reading the
Request Register, bits 4-7 will always read as ones, and bits
0-3 will display the request bits of channels 0-3 respectively.
Request Register
7
7
ALL ONES, READ
WRITE BITS 4-7
6
DON’T CARE,
6
5
5
4
4
3
3
2
2
1
1
0
0
00
01
10
11
XX READBACK
00
01
10
11
XX IF BITS 6 AND 7 = 11
0
1
0
1
00
01
10
11
CHANNEL 0 SELECT
CHANNEL 1 SELECTT
CHANNEL 2 SELECT
CHANNEL 3 SELECT
VERIFY TRANSFER
WRITE TRANSFER
READ TRANSFER
ILLEGAL
AUTOINITIALIZATION DISABLE
AUTOINITIALIZATION ENABLE
ADDRESS INCREMENT SELECT
ADDRESS DECREMENT SELECT
DEMAND MODE SELECT
SINGLE MODE SELECT
BLOCK MODE SELECT
CASCADE MODE SELECT
00
01
10
11
0
1
SELECT CHANNEL 0
SELECT CHANNEL 1
SELECT CHANNEL 2
SELECT CHANNEL 3
RESET REQUEST BIT
SET REQUEST BIT
Spec Number
BIT NUMBER
BIT NUMBER
518058