K4H510638E-TC/LA2 SAMSUNG [Samsung semiconductor], K4H510638E-TC/LA2 Datasheet - Page 14

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K4H510638E-TC/LA2

Manufacturer Part Number
K4H510638E-TC/LA2
Description
Stacked 512Mb E-die DDR SDRAM Specification (x4/x8)
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
AC Timming Parameters & Specifications
DDR SDRAM stacked 512Mb E-die (x4/x8)
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Output Slew Rate Matching Ratio(rise to fall)
Parameter
CL=2.0
CL=2.5
tDQSCK
tWPRES
Symbol
tWPRE
tDQSQ
tRPRE
tDQSS
tDQSH
tSLMR
tRPST
tDQSL
tRRD
tWTR
tRCD
tCCD
tDSH
tDSC
tRFC
tRAS
tDSS
tWR
tRC
tRP
tCK
tCH
tAC
tCL
tHZ
tLZ
tIS
tIH
tIS
tIH
(DDR266@CL=2.0)
-0.75
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
7.5
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
15
60
75
45
15
15
15
1
1
0
-
AA
+0.75
+0.75
120K
Max
+0.75
+0.75
0.55
0.55
1.25
1.5
0.5
1.1
0.6
1.1
12
12
(DDR266@CL=2.0)
-0.75
-0.75
-0.75
-0.75
0.67
Min
0.45
0.45
0.75
0.25
0.35
0.35
7.5
0.9
0.2
1.0
7.5
0.4
0.2
0.9
0.9
0.9
1.0
20
15
15
65
75
45
20
1
1
0
-
A2
+0.75
+0.75
120K
Max
+0.75
+0.75
0.55
0.55
1.25
1.1
1.1
1.5
0.5
0.6
12
12
(DDR266@CL=2.5))
-0.75
-0.75
-0.75
-0.75
0.45
0.45
0.75
0.35
0.67
Min
0.25
0.35
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
65
75
45
20
20
15
15
10
1
1
0
-
Rev. 1.0 July. 2003
B0
DDR SDRAM
+0.75
+0.75
120K
+0.75
+0.75
Max
0.55
0.55
1.25
0.5
1.1
0.6
1.1
1.5
12
12
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
i,5.7~9
i,5.7~9
i, 6~9
i, 6~9
Note
12
3
1
1

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