PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 9

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

2.0 Functional Description
1.
2.
3.
Note: PIO or DMA mode is only controlled by the setting of the DMA__EN bit in the extended-mode MCR register. The device treats CPU and DMA access cycles
While a frame is being transmitted, data must be written to the TX__FIFO at a rate dictated by the transmission speed. If the CPU
or DMA controller fails to meet this requirement, a transmitter underrun will occur, an inverted CRC is appended to the frame be-
ing transmitted, and the frame is terminated with a Stop flag. Data transmission will then stop. Transmission of the inverted CRC
will guarantee that the remote receiving device will receive the frame with a CRC error and will discard it.
Following an underrun condition, data transmission always stops at the next frame boundary. The frame bytes from the point
where the underrun occurred to the end of the frame will not be sent out to the external infrared interface. Nonetheless, they will
be removed from the TX__FIFO by the transmitter and discarded. The underrun indication will be reported only when the trans-
mitter detects the end of frame via one of the methods described above. The software can do various things to recover from an
underrun condition. For example, it can simply clear the underrun condition by writing a 1 into bit 6 of ASCR and re-transmit the
underrun frame later, or it can re-transmit it immediately, before transmitting other frames.
If it chooses to re-transmit the frame immediately, it needs to perform the following steps:
1. Disable DMA controller, if DMA mode was selected.
2. Read the TXFLV register to determine the number of bytes in the TX__FIFO. (This is needed to determine the exact point
3. Reset TX__FIFO.
4. Backup DMA controller registers.
5. Clear Transmitter underrun bit.
6. Re-enable DMA controller.
2.5.2 High Speed Infrared Receive Operation
When the receiver front-end detects an incoming frame, it will start de-serializing the infrared bit stream and load the resulting
data bytes into the RX__FIFO. When the EOF is detected, two or four CRC bytes are appended to the received data, and an EOF
flag is written into the tag section of the RX__FIFO along with the last byte. In the present implementation, the CRC bytes are al-
ways transferred to the RX__FIFO following the data. Additional status information, related to the received frame, is also written
into the RX__FIFO tag section at this time. The status information will be loaded into the LSR register when the last frame byte
reaches the RX__FIFO bottom.
The receiver keeps track of the number of received bytes from the beginning of the current frame. It will only transfer to the
RX__FIFO a number of bytes not exceeding the maximum frame length value which is programmed via the RFRML register in
bank 4. Any additional frame bytes will be discarded. When the maximum frame length value is exceeded, the MAX__LEN error
flag will be set.
Although data transfers from the RX__FIFO to memory can be performed either in PIO or DMA mode, DMA mode should be used
due to the high data rates.
In order to handle back-to-back incoming frames, when DMA mode is selected and an 8237 type DMA controller is used, an
8-level ST__FIFO (Status FIFO) is provided. When an EOF is detected, in 8237 DMA mode, the status and byte count information
for the frame is written into the ST__FIFO. An interrupt is generated when the ST__FIFO level reaches a programmed threshold
or an ST__FIFO time-out occurs.
The CPU uses this information to locate the frame boundaries in the memory buffer where the data, belonging to the received
frames, has been transferred by the 8237 type DMA controller.
During reception of multiple frames, if the RX__FIFO and/or the ST__FIFO fills up, due to the DMA controller or CPU not serving
them in time, one or more frames can be crushed and lost. This means that no bytes belonging to these frames were written to
CPU sets the S__EOT bit before writing the last byte into the TX__FIFO, the byte will be tagged with an EOF indication. When
this byte reaches the TX__FIFO bottom, and is read by the transmitter front-end, a CRC is appended to the transmitted DATA
and the frame is normally terminated.
similarly to the previous method except that the tagging of the last byte of a frame occurs when the DMA controller asserts
the TC signal during the write of the last byte to the TX__FIFO.
of the FEND__MD bit in the IRCR2 register determines whether the Frame Length Counter is effective in the PIO or DMA
mode. The counter is loaded from the Frame Length Register (TFRL) at the beginning of each frame, and it is decremented
as each byte is transmitted. An EOF is generated when the counter reaches zero. When used in DMA mode with an 8237 type
DMA controller, this method allows a large data block to be automatically split into equal-size back-to-back frames, plus a
shorter frame that is terminated by the DMA TC signal, if the block size is not an exact multiple of the frame size.
An option is also provided to stop transmission at the end of each frame. This happens when the transmitter Frame-End stop
mode is enabled (TX__MS bit in the IRCR2 register set to 1). By using this option, the software can send frames of different
sizes without re-initializing the DMA controller for each frame. After transmission of each frame, the transmitter stops and gen-
erates an interrupt. The software loads the length of the next frame into the TFRL register and restarts the transmitter by
clearing the TXHFE bit in the ASCR register.
where the underrun occurred, and whether or not the first byte of a new frame is in the TX__FIFO).
Frame Length Counter. This method can be used when data transfers are performed in either PIO or DMA mode. The value
S__EOT bit (Set End of Transmission). This method is used when data transfers are performed in PIO mode. When the
DMA TC Signal (DMA Terminal Count). This method is used when data transfers are performed in DMA mode. It works
the same except that DMA cycles always access the TX__ or RX__FIFO, regardless of the selected bank. When DMA__EN is set to 1, the CPU can still ac-
cess the TX__FIFO and RX__FIFO. The CPU accesses will, however, be treated as DMA accesses as far as the function of the FEND__MD bit is concerned.
(Continued)
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