PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 28

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PC87108AVJE

Manufacturer Part Number
PC87108AVJE
Description
Advanced UART and Infrared Controller
Manufacturer
NSC [National Semiconductor]
Datasheet
www.national.com
3.0 Architectural Description
B5 ETDLBK – Enable Transmitter Output During Loopback.
B6 Reserved.
B7 BTEST – Baud Generator Test.
3.3.3 LCR/BSR – Link Control/Bank Select Registers
These registers are the same as in bank 0.
3.3.4 EXCR2 – Extended Control Register 2
This register is used to configure the transmitter and receiver FIFOs, and the baud generator prescaler.
Upon reset all bits are set to 0.
B1–0 TF__SIZ [1–0] – TX__FIFO Levels Select.
Bits
Function
Reset State
1. The transmitter and receiver interrupts are fully operational. The modem status interrupts are also fully operational, but the
2. The DMA control signals are fully operational.
3. UART and infrared receiver serial input pins are disconnected. The internal receiver serial inputs are connected to the cor-
4. The UART transmitter serial output pin is forced high and the infrared transmitter serial output pin is forced low, unless the
5. The modem status input pins (DSR , CTS , RI and DCD ) are disconnected. The internal modem status signals, are driven
When set to 1, the transmitter serial output is enabled and functions normally when loopback is selected.
Write 1.
When set to 1, the output of the baud generator is routed to the DTR pin.
interrupts’ sources are now the lower bits of the MCR register. Modem interrupts in infrared modes are disabled unless the
IRMSSL bit in the IRCR2 register is 0. Individual interrupts are still controlled by the IER register bits.
responding internal transmitter serial outputs.
ETDLBK bit is set to 1. In which case they will function normally.
by the lower bits of the MCR register.
These bits select the number of levels for the TX__FIFO.
They are effective only when the FIFOs are enabled.
LOCK
B7
0
res
B6
0
Bits 1–0
FIGURE 16. DMA Control Signals Routing
FIGURE 17. Extended Control Register 2
PRESL1
00
01
1x
B5
0
(Continued)
PRESL0
B4
0
28
RF__SIZ1
TX__FIFO Levels
B3
0
Reserved
16
32
RF__SIZ0
B2
0
TF__SIZ1
B1
0
DS012549-8
TF__SIZ0
B0
0

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