PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 3

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

Table of Contents
TABLE 12. Bank 6 Register Set
TABLE 13. Bank 7 Register Set
TABLE 14. CEIR Demodulator Frequency Ranges in kHz,
Low Speed (RXHSC = 0)
TABLE 15. CEIR Hi-Speed Demodulator Frequency Ranges
in kHz, High-Speed (RXHSC = 1)
TABLE 16. Sharp-IR Demodulator Frequency Ranges in kHz
TABLE 17. Infrared Receiver Input Selection
TABLE 18. Base Address Configuration
TABLE 19. Configuration and GPIO Registers
List of Figures
FIGURE 1. 80-Pin TQFP Package
FIGURE 2. Basic Configuration
FIGURE 3. Register Bank Architecture
FIGURE 4. Interrupt Enable Register
FIGURE 5. Event Identification Register, Non-Extended
Mode
FIGURE 6. Event Identification Register, Extended Mode
FIGURE 7. FIFO Control Register
FIGURE 8. Link Control Register
FIGURE 9. Modem Control Register, Non-Extended Mode
FIGURE 10. Modem Control Register, Extended Mode
FIGURE 11. Link Status Register
FIGURE 12. Modem Status Register
FIGURE 13. Auxiliary Status and Control Register
FIGURE 14. Extended Control Register 1
FIGURE 15. DMA Control Signals Routing
FIGURE 16. Extended Control Register 2
FIGURE 17. Transmit FIFO Level
FIGURE 18. Receive FIFO Level
(Continued)
3
FIGURE 19. Infrared Control Register 1
FIGURE 20. Pipelined Mode Register
FIGURE 21. Infrared Control Register 2
FIGURE 22. Frame Status Byte
FIGURE 23. Infrared Control Register 3
FIGURE 24. MIR Pulse Width Register
FIGURE 25. SIR Pulse Width Register
FIGURE 26. Beginning Flags/Preamble Length Register
FIGURE 27. Infrared Receiver Demodulator Control Regis-
ter
FIGURE 28. Infrared Transmitter Modulator Control Register
FIGURE 29. CEIR Configuration Register
FIGURE 30. Infrared Configuration Register 1
FIGURE 31. Infrared Configuration Register 2
FIGURE 32. Infrared Configuration Register 3
FIGURE 33. Infrared Configuration Register 4
FIGURE 34. Base Address and Interrupt Control Register
FIGURE 35. Control Signals Routing Register
FIGURE 36. Mode Control RegisteMode Control Register
FIGURE 37. GPIO Direction Register
FIGURE 38. GPIO Data Register
FIGURE 39. Testing Specification Standard
FIGURE 40. Clock Timing
FIGURE 41. CPU Read Timing
FIGURE 42. CPU Write Timing
FIGURE 43. DMA Access Timing
FIGURE 44. UART, Sharp-IR and CEIR Timing
FIGURE 45. SIR, MIR and FIR Timing
FIGURE 46. GPIOn and IRSLn Write Timing
FIGURE 47. Reset Timing
FIGURE 48. Thin Plastic Quad Flat Pack
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