PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 51

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

Symbol
UART AND INFRARED INTERFACE TIMING
F
t
t
t
MISCELLANEOUS TIMING
t
t
t
FJT
FPW
DPW
WOD
MRW
MRF
5.4.1 Timing Table
Note 8: t
IRTXMC and RCCFG registers.
Note 9: t
IRTXMC and RCCFG registers.
Note 10: t
receiver. These time values are determined by the content of register IRRXDC and the setting of bit RXHSC in the RCCFG register.
Note 11: t
Note 12: t
Note 13: The receiver pulse width requirements for various jitter values can be obtained by assuming a linear pulse-width/jitter relationship. For example, if the jitter
is
T
DRT
5.4.2 Timing Diagrams
A
±
= 0˚C to 70˚C, V
10 ns, the width of a single pulse must fall between 84 and 165 ns.
CWN
CPN
BTN
MWN
MMIN
Figure 46
Figure 46
Figure 47
Figure 48
Figure 48
Figure
is the nominal period of the modulation signal for Sharp-IR and Consumer-IR modes. It is determined by the MCFR [4–0] and TXHSC bits in the
is the nominal pulse width of the modulation signal for Sharp-IR and Consumer-IR modes. It is determined by the MCPW [2–0] and TXHSC bits in the
is the nominal bit time in UART, Sharp-IR, SIR, MIR and CEIR modes.
is the nominal pulse width for MIR mode. It is determined by the MPW [3–0] and MDRS bits in the MIR__PW and IRCR2 registers.
and t
MMAX
DD
define the time range within which the period of the incoming subcarrier signal has to fall in order for the signal to be accepted by the
FIR Data Rate Tolerance.
Percent of
Nominal Data Rate
FIR Leading Edge Jitter.
Percent of
Nominal Chip Duration
FIR Single Pulse Width
(Note 13)
FIR Double Pulse Width
(Note 13)
IRSLn, GPIOn, RTS and DTR Delay from Write
Inactive
Master Reset Pulse Width
Output Signals Floating from Reset Active
= 5V
±
10% or 3.3V
(Continued)
±
Parameter
10%, V
FIGURE 41. Clock Timing
SS
= 0V
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver Leading
Edge Jitter = 0 ns
Transmitter
Receiver Leading
Edge Jitter = 0 ns
Receiver Leading
Edge Jitter
=
Receiver Leading
±
25 ns
51
Edge Jitter
=
±
25 ns
DS012549-5
1000
Min
115
115
205
215
80
90
±
±
±
±
0.01%
0.01%
25.0%
Max
4.0%
135
175
150
135
300
310
700
60
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Units
ns
ns
ns
ns
ns
ns
ns
ns
ns