ZL50232GDC ZARLINK [Zarlink Semiconductor Inc], ZL50232GDC Datasheet - Page 6

• Manufacturer Part Number: ZL50232GDC
• Description: 32 Channel Voice Echo Canceller
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

1.0
The ZL50232 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers,
Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or
Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64 ms
echo cancellation, which run independently on different channels. In Extended Delay configuration, a group of
echo cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (A & B). In
Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel, providing full-duplex 64 ms echo cancellation.
Pin Description (continued)
PLLVss1
PLLVss2
PLLV
RESET R3
Name
TRST
TMS
TDO
Fsel
TCK
Pin
TDI
DD
Device Overview
H2
K3
K4
M2
M1
N1
P1
N2
208-Ball LBGA
Pin #
92
97, 95
96
1
2
3
4
6
8
100 Pin
LQFP
Zarlink Semiconductor Inc.
Frequency select (Input). This input selects the Master Clock
frequency operation. When Fsel pin is low, nominal 19.2 MHz
Master Clock input must be applied. When Fsel pin is high,
nominal 9.6 MHz Master Clock input must be applied.
PLL Ground. Must be connected to V
PLL Power Supply. Must be connected to V
Test Mode Select (3.3 V Input). JTAG signal that controls the
state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
Test Serial Data In (3.3 V Input). JTAG serial test instructions
and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data Out (Output). JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in high impedance
state when JTAG scan is not enabled.
Test Clock (3.3 V Input). Provides the clock to the JTAG test
logic.
Test Reset (3.3 V Input). Asynchronously initializes the JTAG
TAP controller by putting it in the Test-Logic-Reset state. This pin
should be pulsed low on power-up or held low, to ensure that the
ZL50232 is in the normal functional mode. This pin is pulled by
an internal pull-down when not driven.
Device Reset (Schmitt Trigger Input). An active low resets the
device and puts the ZL50232 into a low-power stand-by mode.
When the RESET pin is returned to logic high and a clock is
applied to the MCLK pin, the device will automatically execute
initialization routines, which preset all the Main Control and
Status Registers to their default power-up values.
ZL50232
6
Description
SS
DD2
= 1.8 V
Data Sheet