ZL50232GDC ZARLINK [Zarlink Semiconductor Inc], ZL50232GDC Datasheet - Page 37

• Manufacturer Part Number: ZL50232GDC
• Description: 32 Channel Voice Echo Canceller
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Main Control Register 1 (EC Group 1)
Main Control Register 2 (EC Group 2)
Main Control Register 3 (EC Group 3)
Main Control Register 4 (EC Group 4)
Main Control Register 5 (EC Group 5)
Main Control Register 6 (EC Group 6)
Main Control Register 7 (EC Group 7)
Main Control Register 8 (EC Group 8)
Main Control Register 9 (EC Group 9)
Main Control Register 10 (EC Group 10)
Main Control Register 11 (EC Group 11)
Main Control Register 12 (EC Group 12)
Main Control Register 13 (EC Group 13)
Main Control Register 14 (EC Group 14)
Main Control Register 15 (EC Group 15)
Bit 7
Unused
Unused
Format
MTDBI
MTDAI
PWUP
Law
Bit 6
Unused
Unused Bits.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711)
PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM
code
A/µ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, select µ-Law companded
PCM code
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo cancellers A and B execute their initialization routine which presets their registers, Base
Address+00
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their specific
application.
.
.
hex
Bit 5
Unused
to Base Address+3F
Power-up 00
Functional Description of Register Bits
Bit 4
MTDBI
Zarlink Semiconductor Inc.
hex
hex
ZL50232
, to default Reset Value and clears the Adaptive Filter
37
Bit 3
MTDAI
Bit 2
Format
R/W Address: 401
R/W Address: 402
R/W Address: 403
R/W Address: 404
R/W Address: 405
R/W Address: 406
R/W Address: 407
R/W Address: 408
R/W Address: 409
R/W Address: 40A
R/W Address: 40B
R/W Address: 40C
R/W Address: 40D
R/W Address: 40E
R/W Address: 40F
Bit 1
Law
Data Sheet
Bit 0
PWUP
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex