ZL50232GDC ZARLINK [Zarlink Semiconductor Inc], ZL50232GDC Datasheet - Page 18
ZL50232GDC
Manufacturer Part Number
ZL50232GDC
Description
32 Channel Voice Echo Canceller
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50232GDC.pdf
(41 pages)
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6.5
Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their
respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are
bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section
for description.
The typical power consumption can be calculated with the following equation:
where 0 ≤ Nb_of_groups ≤ 16.
6.6
To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting
the echo canceller in bypass mode for at least one frame (125 µs) and then enabling adaptation.
Since the Narrow Band Detector is “ON” regardless of the functional state of Echo Canceller it is recommended that
the Echo cancellers are reset before any call progress tones are applied.
Power Management
Call Initialization
Figure 11 - Power Up Sequence Flow Diagram
Delay 1000 ns
Reset High
Reset Low
P
Hardware
C
= 9 * Nb_of_groups + 3.6, in mW
Zarlink Semiconductor Inc.
System Powerup
Reset Held Low
ZL50232
MCLK Active
ECAN Ready
Delay 500
Delay 100
Delay 500
Reset High
Reg. Reset
18
µ
µ
µ
s
s
s
Software
Delay 250
PWUP to “1”
PWUP to “0”
µ
s
Data Sheet
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