ZL50232GDC ZARLINK [Zarlink Semiconductor Inc], ZL50232GDC Datasheet - Page 32

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ZL50232GDC

Manufacturer Part Number
ZL50232GDC
Description
32 Channel Voice Echo Canceller
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in
16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high
byte is in Register 2 and the low byte is in Register 1.
These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The information
is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The
high byte is in Register 2 and the low byte is in Register 1.
RP15
SP15
Bit 7
Bit 7
RP7
Bit 7
Bit 7
SP7
Power-up
Power-up
Power-up
Power-up
N/A
N/A
N/A
N/A
RP14
Bit 6
Bit 6
RP6
SP14
Bit 6
Bit 6
SP6
RP13
Bit 5
Bit 5
RP5
SP13
Bit 5
Bit 5
SP5
ECA: Rin Peak Detect Register 2 (RP)
ECB: Rin Peak Detect Register 2 (RP)
ECA: Rin Peak Detect Register 1 (RP)
ECB: Rin Peak Detect Register 1 (RP)
ECA: Sin Peak Detect Register 2 (SP)
ECB: Sin Peak Detect Register 2 (SP)
ECA: Sin Peak Detect Register 1 (SP)
ECB: Sin Peak Detect Register 1 (SP)
Functional Description of Register Bits
Functional Description of Register Bits
RP12
Bit 4
Bit 4
RP4
Zarlink Semiconductor Inc.
SP12
Bit 4
Bit 4
SP4
ZL50232
32
RP11
Bit 3
Bit 3
RP3
SP11
Bit 3
Bit 3
SP3
RP10
Bit 2
Bit 2
RP2
SP10
Bit 2
Bit 2
SP2
0D
2D
0C
2C
0F
2F
0E
2E
Bit 1
Bit 1
RP9
RP1
hex
hex
hex
hex
Bit 1
SP9
Bit 1
SP1
hex
hex
Read Address:
Read Address:
Read Address:
Read Address:
hex
hex
Read Address:
Read Address:
Read Address:
Read Address:
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
Data Sheet
Bit 0
RP8
Bit 0
RP0
Bit 0
SP8
Bit 0
SP0

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