ZL50232GDC ZARLINK [Zarlink Semiconductor Inc], ZL50232GDC Datasheet - Page 26

• Manufacturer Part Number: ZL50232GDC
• Description: 32 Channel Voice Echo Canceller
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

8.0
Bypass
AdpDis
Bypass
AdpDis
INJDis
INJDis
Reset
Reset
Reset
Reset
ExtDl
BBM
BBM
Bit 7
PAD
Bit 7
PAD
0
1
0
Register Description
When high, the power-up initialization is executed. This presets all register bits including
this bit and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low noise injection is enabled.
When high, the Back to Back configuration is enabled. When low, the Normal
configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at
the same time. Always set both BBM bits of the two echo cancellers (Control Register 1)
of the same group to the same logic value to avoid conflict.
When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the
Gains register controls the signal levels.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The
Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low,
output data on both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
When high, Echo Cancellers A and B of the same group are internally cascaded into one
128 ms echo canceller. When low, Echo Cancellers A and B of the same group operate
independently.
When high, the power-up initialization is executed which presets all register bits including
this bit and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low, noise injection is enabled.
When high, the Back to Back configuration is enabled. When low, the Normal
configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at
the same time. Always set both BBM bits of the two echo cancellers (Control Register 1)
of the same group to the same logic value to avoid conflict.
When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the
Gains register controls the signal levels.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The
Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low,
output data on both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Control Register 1 (Echo Canceller B) Bit 0 is a reserved bit and should be written “0”.
INJDis
INJDis
Bit 6
Bit 6
Power-up 00
Power-up 02
Echo Canceller A (ECA): Control Register 1
Echo Canceller B (ECB): Control Register 1
BBM
BBM
Bit 5
Bit 5
hex
hex
Functional Description of Register Bits
Functional Description of Register Bits
Zarlink Semiconductor Inc.
Bit 4
PAD
Bit 4
PAD
ZL50232
26
Bypass
Bypass
Bit 3
Bit 3
R/W Address: 00
R/W Address: 20
AdpDis
AdpDis
Bit 2
Bit 2
hex
hex
+ Base Address
+ Base Address
Bit 1
Bit 1
0
1
Data Sheet
ExtDI
Bit 0
Bit 0
0