UPD64084 NEC, UPD64084 Datasheet - Page 27

• Manufacturer Part Number: UPD64084
• Description: THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
• Manufacturer: NEC

11. C SIGNAL OUTPUT PROCESSING BLOCK
adjustment for the C signal submitted to CNR processing.
11.1 C Signal Delay Adjustment
serial bus. This way, the delay of the C signal relative to the Y signal can be set to anywhere between 4 clock pulses
( 280 ns) and +3 clock pulses (+210 ns).
11.2 BPF and Gain Processing
or 1).
After Y/C separation, the C signal output processing block performs delay adjustment, BPF processing, and gain
The delay time of the C signal can be varied in a range between 0 and 7 clock pulses (4f
COUTS on the serial bus can be used to specify whether to insert a BPF. It can also be used to specify the gain ( 2
C signal input
Figure 11-1. C Signal Output Processing Block Diagram
Variable
( 0~ 7)
delay
CDL
Data Sheet S16021EJ2V0DS
BPF
(f
SC
)
COUTS0
2
COUTS1
C signal output
SC
) according to CDL on the
PD64084
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