ATTIny13-12PI ATMEL Corporation, ATTIny13-12PI Datasheet - Page 91

• Manufacturer Part Number: ATTIny13-12PI
• Description: 8-bit AVR Microcontroller with 1K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

ADC Control and Status
Register B – ADCSRB
Digital Input Disable Register
0 – DIDR0
2535B–AVR–01/04
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse-
quently, if the result is left adjusted and no more than 8-bit precision is required, it is
sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is
read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared
(default), the result is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion
Result” on page 88.
• Bits 7, 5..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will
trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no
effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.
Note that switching from a trigger source that is cleared to a trigger source that is set,
will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will
start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trig-
ger event, even if the ADC Interrupt Flag is set
Table 40. ADC Auto Trigger Source Selections
• Bits 5..2 – ADC3D..ADC0D: ADC3..0 Digital Input Disable
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADTS2
0
0
0
0
1
1
1
0
0
R
R
7
–
0
7
–
0
ADTS1
ACME
R/W
0
0
R
6
–
0
6
0
0
0
1
1
0
0
1
ADC0D
R/W
0
0
5
0
R
5
–
0
ADC2D
ADTS0
R/W
0
0
4
0
R
4
–
0
0
1
0
1
0
1
0
.
ADC3D
R/W
0
0
R
3
0
3
–
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter Compare Match A
Timer/Counter Overflow
Timer/Counter Compare Match B
Pin Change Interrupt Request
ADC1D
ADTS2
R/W
R/W
0
0
2
0
2
0
ADTS1
AIN1D
R/W
R/W
0
0
1
0
1
0
ATtiny13
AIN0D
ADTS0
R/W
R/W
0
0
0
0
0
0
ADCSRB
DIDR0
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