ATTIny13-12PI ATMEL Corporation, ATTIny13-12PI Datasheet - Page 72

• Manufacturer Part Number: ATTIny13-12PI
• Description: 8-bit AVR Microcontroller with 1K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter
Prescaler
Prescaler Reset
External Clock Source
72
ATtiny13
The Timer/Counter can be clocked directly by the system clock (by setting the
CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock
frequency equal to system clock frequency (f
the prescaler can be used as a clock source. The prescaled clock has a frequency of
either f
The prescaler is free running, i.e., operates independently of the Clock Select logic of
the Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock
select, the state of the prescaler will have implications for situations where a prescaled
clock is used. One example of prescaling artifacts occurs when the timer is enabled and
clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from
when the timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the T0 pin can be used as Timer/Counter clock
(clk
logic. The synchronized (sampled) signal is then passed through the edge detector. Fig-
ure 36 shows a functional equivalent block diagram of the T0 synchronization and edge
detector logic. The registers are clocked at the positive edge of the internal system clock
(
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 36. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at
least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse
is generated.
Each half period of the external clock applied must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have less
than half the system clock frequency (f
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than f
An external clock source can not be prescaled.
clk
Tn
I/O
T0
clk
). The latch is transparent in the high period of the internal system clock.
). The T0 pin is sampled once every system clock cycle by the pin synchronization
I/O
CLK_I/O
/8, f
D
LE
CLK_I/O
Q
/64, f
Synchronization
D
CLK_I/O
Q
/256, or f
clk_I/O
T
0
ExtClk
pulse for each positive (CSn2:0 = 7) or negative
/2.5.
CLK_I/O
< f
CLK_I/O
clk_I/O
/1024.
). Alternatively, one of four taps from
/2) given a 50/50% duty cycle. Since
D
Q
Edge Detector
2535B–AVR–01/04
Tn_sync
(To Clock
Select Logic)