ATTIny13-12PI ATMEL Corporation, ATTIny13-12PI Datasheet - Page 155

• Manufacturer Part Number: ATTIny13-12PI
• Description: 8-bit AVR Microcontroller with 1K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Instruction Set Summary
2535B–AVR–01/04
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
ORI
EOR
COM
NEG
SBR
CBR
INC
DEC
TST
CLR
SER
BRANCH INSTRUCTIONS
RJMP
IJMP
RCALL
ICALL
RET
RETI
CPSE
CP
CPC
CPI
SBRC
SBRS
SBIC
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
LSR
ROL
Mnemonics
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Rd
Rd,K
Rd,K
Rd
Rd
Rd
Rd
Rd
k
k
Rd,Rr
Rd,Rr
Rd,Rr
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
P,b
P,b
Rd
Rd
Rd
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Operands
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Relative Jump
Indirect Jump to (Z)
Relative Subroutine Call
Indirect Call to (Z)
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare
Compare with Carry
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Description
Rdh:Rdl
Rd
Rd
Rd
if (Rd = Rr) PC
if (Rr(b)=0) PC
if (SREG(s) = 1) then PC PC+k + 1
if (SREG(s) = 0) then PC PC+k + 1
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (T = 1) then PC
if (V = 1) then PC
if ( I = 1) then PC
I/O(P,b)
Rd
Rd
Rd
Rd
Rd
Rdh:Rdl
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
PC
PC
PC
PC
PC
PC
Rd
Rd
Rd
if (Rr(b)=1) PC
if (P(b)=0) PC
if (P(b)=1) PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N
if (N
if (H = 1) then PC
if (H = 0) then PC
if (T = 0) then PC
if (V = 0) then PC
if ( I = 0) then PC
I/O(P,b)
Rd(n+1)
Rd(n)
Rd(0) C,Rd(n+1)
Rr
Rr
K
Rd + Rr
Rd + Rr + C
Rd - Rr
Rd - K
Rd - Rr - C
Rd - K - C
Rd Rr
Rd K
Rd v Rr
Rd v K
Rd
0xFF
0x00
Rd v K
Rd (0xFF - K)
Rd + 1
Rd
Rd Rd
0xFF
PC + k + 1
Z
PC + k + 1
Z
STACK
STACK
Rd
V= 0) then PC
V= 1) then PC
Rd(n+1), Rd(7)
C
1
0
Rdh:Rdl + K
Rdh:Rdl - K
1
Rd(n), Rd(0)
Rr
Rd
Rd
Rd
Operation
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
Rd(n),C Rd(7)
PC + k + 1
PC + k + 1
0
0
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
None
I
None
None
Flags
ATtiny13
#Clocks
1/2/3
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
4
4
1
1
1
2
2
1
1
1
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