XR16L2751CM EXAR [Exar Corporation], XR16L2751CM Datasheet - Page 9

• Manufacturer Part Number: XR16L2751CM
• Description: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
• Manufacturer: EXAR [Exar Corporation]

XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
The 2751 can accept up to 5V inputs when operating at 3.3V or 2.5V. But note that if the 2751 is operating at
2.5V, its V
is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.
The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to
their default state (see
reset function in the device.
The XR16L2751 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x0A for the
XR16L2751 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.
The UART provides the user with the capability to bi-directionally transfer information between an external CPU
and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a logic 0
on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send transmit
data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power up
initialization to write to the same internal registers, but do not attempt to read from both UARTs simultaneously.
Individual channel select functions are shown in
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the 2751 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in
the Motorola Bus Mode.
Each UART channel in the 2751 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single 16C550
and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status and
control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers, (LSR/LCR),
modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM),
and an user accessible Scratchpad register (SPR).
2.2
2.3
2.4
2.5
2.6
5-Volt Tolerant Inputs
Device Hardware Reset
Device Identification and Revision
Channel A and B Selection
Channel A and B Internal Registers
OH
may not be high enough to meet the requirements of the V
Table
See Table
17). An active pulse of longer than 40 ns duration will be required to activate the
CS#
T
T
CSA#
1
0
0
ABLE
ABLE
1
0
1
0
2.
1: C
2: C
N/A
A3
0
1
HANNEL
HANNEL
CSB#
1
1
0
0
Table
A
A
AND
AND
1.
9
Channel A selected
Channel B selected
UART de-selected
Channel A and B selected
B S
B S
Channel A selected
Channel B selected
F
UART de-selected
UNCTION
ELECT IN
ELECT IN
F
UNCTION
16 M
68 M
IH
of a CPU or a serial transceiver that
ODE
ODE
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áç
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