XR16L2751CM EXAR [Exar Corporation], XR16L2751CM Datasheet
XR16L2751CM
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XR16L2751CM Summary of contents
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TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE SEPTEMBER 2002 GENERAL DESCRIPTION 1 The XR16L2751 (2751 low voltage dual universal asynchronous receiver and transmitter (UART) with 5 Volt tolerant inputs. The device includes 2 additional capabilities XR16L2750: ...
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... TXA TXB OP2B# CSA# CSB# PWRSAVE RXB RXA TXRDYB# TXA TXB OP2B# CS# A3 PWRSAVE ORDERING INFORMATION P N ART UMBER XR16L2751CM XR16L2751IM 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE XR16L2751 6 48-pin TQFP 7 (16 Mode ) XR16L2751 ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 PIN DESCRIPTIONS Pin Description 48-TQFP N T AME YPE DATA BUS INTERFACE A2:A0 26,27,28 I Address data lines [2:0]. These 3 address lines select one ...
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Pin Description 48-TQFP N T AME YPE RXRDYA UART channel A Receiver Ready (active low). This output provides the RX FIFO/ RHR status for receive channel A. TXRDYB UART ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 Pin Description 48-TQFP N T AME YPE RXB 4 I UART channel B Receive Data or infrared receive data. Normal receive data input must idle ...
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Pin Description 48-TQFP N T AME YPE HDCNTL Auto RS-485 half-duplex direction output enable for channel A and B (active low). Connect this pin to VCC for normal RTS# A/B function ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has to set FCTR[ This pin is normally high ...
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F 3. XR16L2751 T I IGURE YPICAL NTEL IOR# IOW # UART_CSA# UART_CSB# UART_INTA UART_INTB TXRDYA# RXRDYA# TXRDYB# RXRDYB# UART_RESET ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 2.2 5-Volt Tolerant Inputs The 2751 can accept inputs when operating at 3.3V or 2.5V. But note that if the 2751 is operating at 2.5V, ...
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Beyond the general 16C2550 features and capabilities, the 2751 offers enhanced feature registers (EFR, Xon/ Xoff 1, Xon/Xoff 2, FCTR, TRG, EMSR, FC) that provide automatic RTS and CTS hardware flow control, Xon/ Xoff software flow ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 2.9 Crystal Oscillator or External Clock Input The 2751 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The ...
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BRG. The BRG further divides this clock by a programmable divisor between 1 and (2 -1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 2.11 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts ...
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IGURE RANSMITTER PERATION IN Transmit Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control 16X or 8X Clock (EMSR bit-7) 2.12 RECEIVER ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0 IGURE ECEIVER PERATION IN NON 16X or 8X Clock (EMSR bit-7) Receive Data Byte and Errors F 10 IGURE ECEIVER PERATION IN ...
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Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 F 11. A RTS CTS F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin ...
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Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 2751 will halt transmission (TX) as ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 2.19 Infrared Mode The 2751 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the ...
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Sleep Mode with Auto Wake-Up and PowerSave Feature The 2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave features is included to reduce power consumption when the device is ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 2.21 Internal Loopback The 2751 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic ...
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UART INTERNAL REGISTERS Each of the UART channel in the 2751 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The complete ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit-7 ...
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T 9: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DLL RD/WR Bit DLM RD/WR Bit ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 4.4 Interrupt Enable Register (IER) - Read/Write The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These ...
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IER[4]: Sleep Mode Enable (requires EFR bit Logic 0 = Disable Sleep Mode (default). Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details. IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0 ABLE P ISR R RIORITY EGISTER EVEL ...
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FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. Logic transmit FIFO reset (default). Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 T 11: T ABLE RANSMIT AND FCTR FCTR FCR FCR ...
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LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and RX Parity Select Parity or ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0, state). ...
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MCR[6]: Infrared Encoder/Decoder Enable Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default) Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the infrared encoder/decoder. ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle set to logic 0 whenever either the ...
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MSR[7]: CD Input Status CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[6]: LSR Interrupt Mode ...
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Device Revision Register (DREV) - Read Only This register contains the device revision information. For example, 0x01 means revision A. Prior to reading this register, DLL and DLM should be set to 0x00. 4.17 Trigger ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 FCTR[6]: Scratchpad Swap Logic 0 = Scratchpad register is selected as general read and write register. ST16C550 compatible mode. Logic 1 = FIFO Count register (Read-Only), Enhanced Mode ...
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EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. After modifying any enhanced bits, EFR bit-4 can ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 4.21 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. For ...
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ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation ELECTRICAL CHARACTERISTICS TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) DC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 asleep. Floating inputs may result in sleep currents in the mA range. For Powersave, the UART internally isolates all of these inputs therefore not requiring them to remain ...
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AC ELECTRICAL CHARACTERISTICS TA (-40 + YMBOL ARAMETER T Delay To Reset Interrupt From RSI IOR# T Delay From Stop To Set Inter- SSI rupt ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0 IGURE ODEM NPUT UTPUT IOW # Active IOW RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI ...
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F 16 IGURE ODE NTEL ATA A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ODE NTEL ATA A0-A2 Valid Address ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0 IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# T RWS R/W# T RDA D0- ...
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F 20 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX S D0:D7 S D0:D7 Stop Bit INT T SSR RXRDY# First Byte is Received in ...
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F 24 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO TXRDY IOW# ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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XR16L2751 REVISION HISTORY Date Revision November 2001 Rev P1.0.0 Prelim data sheet. March 2002 Rev P1.1.0 Corrected INT output descriptions and reset state. Clarified MCR bit-3 descrip- tion. Added 68 Mode (Motorola) Data bus timing specs. Renamed Sclk to Bclk. ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE REV. 1.0.0 GENERAL DESCRIPTION .................................................................................................1 A .............................................................................................................................................1 PPLICATIONS F ...................................................................................................................................................1 EATURES F 1. XR16L2751 B D ................................................................................................................................................. 1 IGURE LOCK IAGRAM ............................................................................................................................................................. 2 IGURE IN ...
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ECEIVE OLDING EGISTER 4 RANSMIT OLDING EGISTER 4 AUD ATE ENERATOR IVISORS 4 NTERRUPT NABLE EGISTER 4.4.1 IER versus Receive FIFO Interrupt ...