XR16L2751CM EXAR [Exar Corporation], XR16L2751CM Datasheet - Page 5

• Manufacturer Part Number: XR16L2751CM
• Description: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
• Manufacturer: EXAR [Exar Corporation]

XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
Pin Description
ANCILLARY SIGNALS
PwrSave
CLKSEL
DSRB#
RTSB#
CTSB#
DTRB#
OP2B#
16/68#
XTAL1
XTAL2
CDB#
N
RIB#
RXB
AME
48-TQFP
P
22
23
35
20
16
21
13
14
12
24
25
IN
4
9
#
T
YPE
O
O
O
O
I
I
I
I
I
I
I
I
I
UART channel B Receive Data or infrared receive data. Normal receive data input
must idle at logic 1 condition. The infrared receiver pulses typically idles at logic 0 but
can be inverted by software control prior going in to the decoder, see MCR[6] and
FCTR[2].
UART channel B Request-to-Send (active low) or general purpose output. This port
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3] and EMSR[3].
UART channel B Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
UART channel B Data-Terminal-Ready (active low) or general purpose output.
UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART
UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART
UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
Output Port 2 Channel B - The output state is defined by the user and through the
software setting of MCR[3]. When MCR[3] is set to a logic 1, INTB is set to the level
mode and OP2B# output to a logic 0. When MCR[3] is set to a logic 0, INTB is set to
the three state mode and OP2B# to a logic 1. See MCR[3]. This output must not be
used as a general output when the interrupt output is used else it will disturb the
INTB output functionality.
Crystal or external clock input. This input is not 5V tolerant.
Crystal or buffered clock output. This output may be use to drive a clock buffer which
can drive other device(s).
PowerSave (active high). This feature isolates the 2751’s data bus interface from the
host preventing other bus activities that cause higher power drain during sleep mode.
See Sleep Mode with Auto Wake-up and PowerSave Feature section for details.
Intel or Motorola Bus Select.
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will operate in the Intel bus
type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will operate in the
Motorola bus type of interface.
Baud-Rate-Generator Input Clock Prescaler Select for channel A and B. This input is
only sampled during power up or a reset. Connect to VCC for divide by 1 (default)
and GND for divide by 4. MCR[7] can override the state of this pin following a reset or
initialization. See MCR bit-7 and
5
Figure 6
D
ESCRIPTION
in the Baud Rate Generator section.
áç
áç
áç
áç