XR16L2751CM EXAR [Exar Corporation], XR16L2751CM Datasheet - Page 12

• Manufacturer Part Number: XR16L2751CM
• Description: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
• Manufacturer: EXAR [Exar Corporation]

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prescaler goes to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (2
-1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter
for data bit shifting and receiver for data sampling. The BRG divisor defaults to the maximum baud rate (DLL =
0x01 and DLM = 0x00) upon power up.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
clock at 16X sampling rate clock rate. A 16X sampling clock is typically used. However, user can select the 8X
sampling clock rate mode (EMSR bit-7=0) to double the operating data rate. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
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O
UTPUT
MCR Bit-7=1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16XMode [EMSR bit-7] = 1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with 16XMode [EMSR bit-7] = 0
115.2k
230.4k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Data Rate
F
T
IGURE
ABLE
X T A L 1
X T A L 2
O
UTPUT
Table 6
6. B
6: T
MCR Bit-7=0
(
DEFAULT
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
YPICAL DATA RATES WITH A
2400
4800
9600
AUD
400
Data Rate
shows the standard data rates available with a 14.7456 MHz crystal or external
R
C rysta l
B u ffe r
)
O sc/
ATE
G
Clock (Decimal)
D
ENERATOR AND
IVISOR FOR
2304
384
192
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
96
48
24
12
6
4
2
1
D ivid e b y 4
D ivid e b y 1
P re sca le r
P re sca le r
16x
14.7456 MH
P
D
12
RESCALER
IVISOR FOR
Clock (HEX)
M C R B it-7 = 0
M C R B it-7 = 1
(d e fa u lt)
900
180
C0
0C
60
30
18
06
04
02
01
Z CRYSTAL OR EXTERNAL CLOCK
16x
B a u d R a te
D L L a n d D L M
G e n e ra to r
R e g iste rs
L o g ic
V
ALUE
P
ROGRAM
DLM
09
01
00
00
00
00
00
00
00
00
00
(HEX)
R a te C lo ck to
T ra n sm itte r
S a m p lin g
V
1 6 X
ALUE
P
ROGRAM
DLL
C0
0C
00
80
60
30
18
06
04
02
01
(HEX)
XR16L2751
D
E
ATA
REV. 1.0.0
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)
16