XR17L154CV EXAR [Exar Corporation], XR17L154CV Datasheet - Page 44

• Manufacturer Part Number: XR17L154CV
• Description: 3.3V PCI BUS QUAD UART
• Manufacturer: EXAR [Exar Corporation]

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EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the
new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
EFR[5]: Special Character Detect Enable
EFR[6]: Auto RTS or DTR Flow Control Enable
RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/DTR
is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS/DTR# will de-assert to a logic 1 at the next upper trigger or selected hysteresis level. RTS/DTR# will
return to a logic 0 when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits
4-7). The RTS# or DTR# output must be asserted (logic 0) before the auto RTS/DTR can take effect. The
selection for RTS# or DTR# is through MCR bit-2. RTS/DTR# pin will function as a general purpose output
when hardware flow control is disabled.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS or DSR Flow Control.
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DISCONTINUED
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with ST16C554 mode (default).
Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are enabled.
Logic 0 = Special Character Detect Disabled. (default)
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit for the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt.
Logic 0 = Automatic RTS/DTR flow control is disabled. (default)
Logic 1 = Enable Automatic RTS/DTR flow control.
Logic 0 = Automatic CTS/DSR flow control is disabled. (default)
Logic 1 = Enable Automatic CTS/DSR flow control. Transmission stops when CTS/DSR# pin de-asserts to
logic 1. Transmission resumes when CTS/DSR# pin returns to a logic 0. The selection for CTS# or DSR# is
through MCR bit-2.
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3.3V PCI BUS QUAD UART
XR17L154
REV. 1.1.0