XR17L154CV EXAR [Exar Corporation], XR17L154CV Datasheet - Page 31

• Manufacturer Part Number: XR17L154CV
• Description: 3.3V PCI BUS QUAD UART
• Manufacturer: EXAR [Exar Corporation]

XR17L154
3.3V PCI BUS QUAD UART
REV. 1.1.0
Receive Holding Register (RHR)
The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register
(RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this
register whenever a data byte is transferred from the RSR. RHR also part of the receive FIFO of 64 bytes by
11-bit wide, 4 extra bits are for the error tags to be in LSR register. When the FIFO is enabled by FCR bit-0, it
acts as the first-out register of the FIFO as new data are put over the first-in register. The receive FIFO pointer
is bumped after the RHR register is read. Also, the error tags associated with the data byte are immediately
updated onto the line status register (LSR) bits 1-4.
F
F
4.8
4.7.1
4.7.2
IGURE
IGURE
( 8 X M O D E R e g is t e r )
Receive Data
Byte and Errors
16X or 8X Sampling
Clock (8XMODE Reg.)
a n d E r r o r s
D a ta B y t e
1 6 X o r 8 X C lo c k
R e c e iv e
14. R
15. R
Registers
64 bytes by 11-
bit wide FIFO
Receiver Operation with FIFO
Receiver Operation in non-FIFO Mode
ECEIVER
ECEIVER
O
O
PERATION IN NON
PERATION IN
L S R b it s
F la g s in
Receive Data Shift
E r r o r
4 : 1
Register (RSR)
Receive Data
Receive
(64-byte)
R e c e iv e D a t a S h if t
FIFO
Data
FIFO
R e g is t e r ( R S R )
H o ld in g R e g is t e r
-FIFO M
R e c e iv e D a t a
AND
( R H R )
F
Data falls to 40
FIFO Trigger=48
Data fills to 56
Validation
Data Bit
LOW
ODE
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
C
31
ONTROL
RTS#/DTR# re-asserts when data falls below the
trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
V a lid a t io n
RHR Interrupt (ISR bit-2) is programmed at
FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
D a ta B it
M
ODE
R H R In te r r u p t ( I S R b it - 2 )
Receive Data Characters
R e c e iv e D a t a C h a r a c t e r s
DISCONTINUED
áç
áç
áç
áç
R X F I F O
RXFIFO1