XR17L154CV EXAR [Exar Corporation], XR17L154CV Datasheet - Page 19

• Manufacturer Part Number: XR17L154CV
• Description: 3.3V PCI BUS QUAD UART
• Manufacturer: EXAR [Exar Corporation]

XR17L154
3.3V PCI BUS QUAD UART
REV. 1.1.0
MPIOSEL [7:0] - (default 0xFF)
Multipurpose input/output pin select. This register defines the functions of the pins. A logic 1 (default) defines
the pin for input and a logic "0" for output.
The L154 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to
the Baud Rate Generators (BRG) in each of the 4 UARTs, the 16-bit general purpose timer/counter and
internal logics. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output.
Caution: The XTAL1 input is not 5V tolerant. See Programmable Baud Rate Generator in the UART section for
programming details.
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant with
10-22 pF capacitance load, 100ppm) connected externally between the XTAL1 and XTAL2 pins (see
Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal 8 baud rate generators
for standard or custom rates. Typically, the oscillator connections are shown in
oscillator circuit please see application note DAN108 on EXAR’s web site.
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel in the device configuration register set
to ease programming. These registers support 8,
increases the data transfer rate on the PCI bus. Additionally, a special register location provides receive data
byte with its associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register
(LSR) content in the UART channel register is paired along with the data byte. This operation further facilitates
data unloading with the error flags without having to read the LSR register separately. Furthermore, the
XR17L154 supports PCI burst mode for read/write operation of up to 64 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error flags before reading the data
byte.
2.0 CRYSTAL OSCILLATOR / BUFFER
3.0 TRANSMIT AND RECEIVE DATA
F
IGURE
MPIO7
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
7. T
MPIO6
Multipurpose Input/Output Selection
YPICAL OSCILLATOR CONNECTIONS
2 2 -4 7 pF
X T A L1
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
C 1
MPIOSEL Register
R =3 0 0 K to 4 00 K
1 4 .7 45 6
16,
M H z
19
24 and 32 bits wide format. In the 32-bit format, it
2 2 -4 7 pF
X T A L2
C 2
Figure
DISCONTINUED
7. For further reading on
áç
áç
áç
áç
Figure
7).