XR17L154CV EXAR [Exar Corporation], XR17L154CV Datasheet - Page 12

• Manufacturer Part Number: XR17L154CV
• Description: 3.3V PCI BUS QUAD UART
• Manufacturer: EXAR [Exar Corporation]

GLOBAL INTERRUPT REGISTER (DWORD) - [default 0x00-00-00-00]
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The XR17L154 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is a 4-bit indicator in INT0 register representing the 4
channels with the first 4 bits representing each channel from 0 to 3. This permits the interrupt routine to quickly
vector and serve that UART channel and determine the source(s) in each individual routines. INT0 bit-0
represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or modem port
status requires service. Other bits in the INT0 register provide indication for the other channels with bit-3
representing UART channel 4 respectively, bits 4 to 7 are reserved and remain at logic zero.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1 and INT2 registers provide the 12-bit interrupt status
for all 4 channels. Bits 8, 9 and 10 representing channel 0 and bits 17,18 and 19 representing channel 3
respectively. Bits 20 to 31 are reserved and remain at logic zero. All 4 channel interrupts status are available
with a single DWORD read operation. This feature allows the host quickly vectors and serves the interrupts,
reducing service interval, hence, reduce host bandwidth requirement.
All bits start up zero. A special interrupt condition is generated by the L154 upon awakening from sleep after all
4 channels were put to sleep mode earlier.
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-3
indicates channel 3. Logic one indicates the channel N [3:0] has called for service. Bits 4 to 7 are reserved and
remain at logic zero The interrupt bit clears after reading the appropriate register of the interrupting channel
register, see Interrupt Clearing section.
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DISCONTINUED
1.2.1
0x08C-08F
0x088-08B
0x080
0x084-087
0x090-093
A
DDRESS
INT3 [31:24]
-
083
The Interrupt Status Register
T
ABLE
ANCILLARY1 (read/write)
ANCILLARY2 (read-only)
INTERRUPT (read-only)
TIMER (read/write)
MPIO (read/write)
4: D
R
EGISTER
INT0 register provides status for each channel
EVICE
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
R s vd
C
Individual U A R T C hannel Interrupt S tatus
ONFIGURATION
INT2 [23:16]
R s vd R s vd R s vd
Figure 4
B
YTE
TIMERMSB
IN T0 R egister
MPIOSEL
MPIOINT
SLEEP
INT3
R
3 [31:24]
shows the 4-byte interrupt register and its make up.
EGISTERS SHOWN IN
12
C h-3 C h-2 C h-1 C h-0
B
YTE
TIMERLSB
MPIOINV
INT1 [15:8]
RESET
REGB
INT2
2 [23:16]
DWORD
B
YTE
(reserved)
(reserved)
3.3V PCI BUS QUAD UART
MPIO3T
ALIGNMENT
TIMER
REGA
DVID
INT1
1 [15:8]
INT0 [7:0]
B
TIMERCNTL
YTE
8XMODE
MPIOLVL
XR17L154
DREV
INT0
REV. 1.1.0
0 [7:0]