XR16C850CM EXAR [Exar Corporation], XR16C850CM Datasheet - Page 37

• Manufacturer Part Number: XR16C850CM
• Description: 2.97V TO 5.5V UART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

xr
REV. 2.3.1
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Count (Write-Only)
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
During Alternate RX/TX FIFO Counter Mode, the first value read after EMSR bits 1-0 have been asserted will
always be the RX FIFO Counter. The second value read will correspond with the TX FIFO Counter. The next
value will be the RX FIFO Counter again, then the TX FIFO Counter and so on and so forth.
EMSR[7:2]: Reserved
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this
is not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 12
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
•
See MCR bit-7 and the baud rate table also.
This register contains the device ID (0x10 for XR16C850). Prior to reading this register, DLL and DLM should
be set to 0x00.
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
4.11
4.12
4.13
4.14
4.15
4.16
4.17
Baud Rate = (Clock Frequency / 16) / Divisor
Enhanced Mode Select Register (EMSR)
FIFO Level Register (FLVL) - Read-Only
Baud Rate Generator Registers (DLL and DLM) - Read/Write
Device Identification Register (DVID) - Read Only
Device Revision Register (DREV) - Read Only
Trigger Level / FIFO Data Count Register (TRG) - Write-Only
FIFO Data Count Register (FC) - Read-Only
for details.
FCTR[6]
0
1
1
1
1
T
ABLE
EMSR[1] EMSR[0] Scratchpad is
12: S
X
0
0
1
1
CRATCHPAD
X
0
1
0
1
37
S
Scratchpad
RX FIFO Counter Mode
TX FIFO Counter Mode
RX FIFO Counter Mode
Alternate RX/TX FIFO
Counter Mode
WAP
2.97V TO 5.5V UART WITH 128-BYTE FIFO
S
ELECTION
XR16C850