XR16C850CM EXAR [Exar Corporation], XR16C850CM Datasheet - Page 24

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XR16C850CM

Manufacturer Part Number
XR16C850CM
Description
2.97V TO 5.5V UART WITH 128-BYTE FIFO
Manufacturer
EXAR [Exar Corporation]
Datasheet

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XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
The 850 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback
mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 16
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
2.22
Internal Loopback
shows how the modem port signals are re-configured. Transmit data from the transmit shift register
F
IGURE
16. I
NTERNAL
Transmit Shift Register
Receive Shift Register
L
OOPBACK
(RHR/FIFO)
(THR/FIFO)
OP1#
RTS#
CTS#
DTR#
DSR#
OP2#
CD#
RI#
MCR bit-4=1
24
VCC
VCC
VCC
VCC
VCC
TX
RX
RTS#
CTS#
DTR#
DSR#
RI#
CD#
OP1#
OP2#
xr
REV. 2.3.1

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