XCF16PVO48C XILINX [Xilinx, Inc], XCF16PVO48C Datasheet - Page 45

• Manufacturer Part Number: XCF16PVO48C
• Description: Platform Flash In-System Programmable Configuration PROMs
• Manufacturer: XILINX [Xilinx, Inc]

DS123 (v2.11.1) March 30, 2007
Product Specification
07/20/04
10/18/04
03/14/05
07/11/05
R
2.4
2.5
2.6
2.7
• Added Pb-free package options VOG20, FSG48, and VOG48.
•
• Section
•
•
•
•
• Table
• Table
• Table
• Table
• Added Virtex-4 LX/FX/SX configuration data to
• Corrected Virtex-II configuration data in
• Corrected Virtex-II Pro configuration data in
• Added Spartan-3L configuration data to
• Added Spartan-3E configuration data to
• Paragraph added to FPGA Master SelectMAP (Parallel) Mode (1),
• Changes to DC Characteristics
• Changes to AC Characteristics
• Minor changes to grammar and punctuation.
• Added explanation of "Preliminary" to DC and AC Electrical Characteristics.
• Move from "Preliminary" to "Product Specification"
• Corrections to Virtex-4 configuration bitstream values
• Minor changes to
• Change to
• Change to
Figure 6, page
(OPTIONAL Daisy-chained Slave FPGAs with different configurations) from DOUT to DIN.
information can be found in Package User Guide.)
Table 2, page
Table 1, page
Table 9, page
Table 10, page
♦ Added most parameter values for XCF08P, XCF16P, XCF32P devices.
♦ Added Footnote (1) to I
♦ Added most parameter values for XCF08P, XCF16P, XCF32P devices.
♦ Expanded Footnote (1) to include XCF08P, XCF16P, XCF32P devices.
♦ Added Footnote (8) through (11) relating to CLKOUT conditions for various parameters.
♦ Added rows to T
♦ Added rows specifying parameters with decompression for T
♦ Added T
♦ Added most parameter values for XCF08P, XCF16P, XCF32P devices.
♦ Separated Footnote (5) into Footnotes (5) and (6) to specify different derivations of T
♦ T
♦ I
♦ V
♦ T
♦ New rows added for T
page 41
depending on whether dual-purpose configuration pins persist as configuration pins, or
become general I/O pins after configuration.
I
OL
IHP.
OER
LC
CCO
"Recommended Operating Conditions," page
"DC Characteristics Over Operating Conditions," page
"AC Characteristics Over Operating Conditions," page
"AC Characteristics Over Operating Conditions When Cascading," page
changed for V
and T
"Absolute Maximum Ratings," page
changed,
added to test conditions for I
"Internal Oscillator," page 10
"CLKOUT," page 10
DDC
HC
3: Removed reference to XC2VP125 FPGA.
1: Broke out V
8: Added clarification of ID code die revision bits.
16, and
9: Deleted T
(setup time with decompression).
modified for 1.8V,
Figure 7, page
Page
CYC
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMs
OL
,
Figure 7, page
specifying parameters for parallel mode.
Page
28.
CEC
CCO
CKMIN2
CCO
and T
28.
specifying no-load conditions.
description
/ V
17,
Page
OEC
(bypass mode) and renamed T
CCJ
Figure 12, page
IL
17: Corrected connection name for FPGA DOUT
, I
,
Table
into two separate columns.
Table
32.
Page
description
Table
ILP
, I
26: Removed parameter T
Table
IHP
2.
2.
31.
2.
Table
,and II
2.
27: Separated V
2.
22,
H
,
Page
Figure 13, page
29:
28:
28. Values modified for I
CLKO
CKMIN1
Page
CCO
, T
SOL
COH
13.
and V
to T
23, and
from table. (T
, T
CKMIN
FF
36:
CCJ
, T
Figure 16,
SF
parameters.
.
.
ILP
CYC
SOL
and
,
45