XCF16PVO48C XILINX [Xilinx, Inc], XCF16PVO48C Datasheet - Page 24

• Manufacturer Part Number: XCF16PVO48C
• Description: Platform Flash In-System Programmable Configuration PROMs
• Manufacturer: XILINX [Xilinx, Inc]

Reset and Power-On Reset Activation
At power up, the device requires the V
monotonically rise to the nominal operating voltage within
the specified V
meet this requirement, then the device might not perform
power-on reset properly. During the power-up sequence,
OE/RESET is held Low by the PROM. Once the required
supplies have reached their respective POR (Power On
Reset) thresholds, the OE/RESET release is delayed (T
minimum) to allow more margin for the power supplies to
stabilize before initiating configuration. The OE/RESET pin
is connected to an external 4.7 kΩ pull-up resistor and also
to the target FPGA's INIT pin. For systems utilizing
slow-rising power supplies, an additional power monitoring
circuit can be used to delay the target configuration until the
system power reaches minimum operating voltages by
holding the OE/RESET pin Low. When OE/RESET is
released, the FPGA’s INIT pin is pulled High allowing the
FPGA's configuration sequence to begin. If the power drops
below the power-down threshold (V
I/O Input Voltage Tolerance and Power Sequencing
The I/Os on each re-programmable Platform Flash PROM
are fully 3.3V-tolerant. This allows 3V CMOS signals to
connect directly to the inputs without damage. The core
power supply (V
output power supply (V
signals can be applied in any order.
DS123 (v2.11.1) March 30, 2007
Product Specification
200 µs ramp
V
CCINT
V
V
R
CCPOR
CCPD
CCINT
CCINT
rise time. If the power supply cannot
), JTAG pin power supply (V
CCO
), and external 3V CMOS I/O
Figure 14: Platform Flash PROM Power-Up Requirements
T
CCPD
OER
CCINT
Recommended Operating Range
), the PROM resets
Delay or Restart
Configuration
power supply to
CCJ
),
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMs
OER
T
OER
and OE/RESET is again held Low until the after the POR
threshold is reached. OE/RESET polarity is not
programmable. These power-up requirements are shown
graphically in
For a fully powered Platform Flash PROM, a reset occurs
whenever OE/RESET is asserted (Low) or CE is
deasserted (High). The address counter is reset, CEO is
driven High, and the remaining outputs are placed in a
high-impedance state.
Notes:
1. The XCFxxS PROM only requires V
2. The XCFxxP PROM requires both V
Additionally, for the XCFxxS PROM only, when V
supplied at 2.5V or 3.3V and V
I/Os are 5V-tolerant. This allows 5V CMOS signals to connect
directly to the inputs on a powered XCFxxS PROM without
damage. Failure to power the PROM correctly while supplying
a 5V input signal can result in damage to the XCFxxS device.
its POR threshold before releasing OE/RESET.
its POR threshold and for V
recommended operating voltage level before releasing
OE/RESET.
A slow-ramping V
be below the minimum operating
voltage when OE/RESET is released.
In this case, the configuration
sequence must be delayed until both
V
recommended operating conditions.
CCINT
and V
Figure
CCO
50 ms ramp
CCINT
have reached their
14.
supply may still
CCINT
CCO
T
is supplied at 3.3V, the
to reach the
RST
CCINT
CCINT
TIME (ms)
ds123_21_103103
to rise above
to rise above
CCO
is
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