XCF16PVO48C XILINX [Xilinx, Inc], XCF16PVO48C Datasheet - Page 13

• Manufacturer Part Number: XCF16PVO48C
• Description: Platform Flash In-System Programmable Configuration PROMs
• Manufacturer: XILINX [Xilinx, Inc]

Serial Daisy Chain
Multiple FPGAs can be daisy-chained for serial
configuration from a single source. After a particular FPGA
has been configured, the data for the next device is routed
internally to the FPGA’s DOUT pin. Typically the data on the
DOUT pin changes on the falling edge of CCLK, although
for some devices the DOUT pin changes on the rising edge
of CCLK. Consult the respective device data sheets for
detailed information on a particular FPGA device. For
clocking the daisy-chained configuration, either the first
FPGA in the chain can be set to Master Serial, generating
the CCLK, with the remaining devices set to Slave Serial
(Figure 8, page
Slave Serial and an externally generated clock can be used
to drive the FPGA's configuration interface
page 17
FPGA Master SelectMAP (Parallel) Mode
(XCFxxP PROM Only)
In Master SelectMAP mode, byte-wide data is written into
the FPGA, typically with a BUSY flag controlling the flow of
data, synchronized by the configuration clock (CCLK)
generated by the FPGA. Upon power-up or reconfiguration,
the FPGA's mode select pins are used to select the Master
SelectMAP configuration mode. The configuration interface
typically requires a parallel data bus, a clock line, and two
control lines (INIT and DONE). In addition, the FPGA’s Chip
Select, Write, and BUSY pins must be correctly controlled or
monitored to enable SelectMAP configuration. The
configuration data is read from the PROM byte by byte on
pins [D0..D7], accessed via the PROM's internal address
counter which is incremented on every valid rising edge of
CCLK. The bitstream data must be set up at the FPGA’s
[D0..D7] input pins a short time before each rising edge of
the FPGA's internally generated CCLK signal. If BUSY is
asserted (High) by the FPGA, the configuration data must
be held until BUSY goes Low. An external data source or
external pull-down resistors must be used to enable the
FPGA's active Low Chip Select (CS or CS_B) and Write
(WRITE or RDWR_B) signals to enable the FPGA's
SelectMAP configuration process.
The Master SelectMAP configuration interface is clocked by
the FPGA’s internal oscillator. Typically, a wide range of
frequencies can be selected for the internally generated
CCLK which always starts at a slow default frequency. The
FPGA’s bitstream contains configuration bits which can
switch CCLK to a higher frequency for the remainder of the
Master SelectMAP configuration sequence. The desired
CCLK frequency is selected during bitstream generation.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained using the persist option.
DS123 (v2.11.1) March 30, 2007
Product Specification
or
Figure 12, page
R
18), or all the FPGA devices can be set to
22).
(Figure 7,
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMs
Connecting the FPGA device to the configuration PROM for
Master SelectMAP (Parallel) Configuration Mode
page
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FPGA Slave SelectMAP (Parallel) Mode
(XCFxxP PROM Only)
In Slave SelectMAP mode, byte-wide data is written into the
FPGA, typically with a BUSY flag controlling the flow of data,
synchronized by an externally supplied configuration clock
(CCLK). Upon power-up or reconfiguration, the FPGA's mode
select pins are used to select the Slave SelectMAP
configuration mode. The configuration interface typically
requires a parallel data bus, a clock line, and two control lines
(INIT and DONE). In addition, the FPGA’s Chip Select, Write,
and BUSY pins must be correctly controlled or monitored to
enable SelectMAP configuration. The configuration data is
read from the PROM byte by byte on pins [D0..D7], accessed
via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The
bitstream data must be set up at the FPGA’s [D0..D7] input
pins a short time before each rising edge of the provided
The DATA outputs of the PROM(s) drive the [D0..D7]
input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s)
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary I
active supply current
Operating Conditions," page
For high-frequency parallel configuration, the BUSY
pins of all PROMs are connected to the FPGA's BUSY
output (when the FPGA has a BUSY pin and when the
use of the FPGA BUSY pin is required). This
connection assures that the next data transition for the
PROM is delayed until the FPGA is ready for the next
configuration data byte. For FPGA BUSY pin
requirements, refer to the appropriate FPGA data sheet
or FPGA family configuration user guide.
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
19):
("DC Characteristics Over
28).
(Figure 9,
CC
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