XCF01SF48 XILINX [Xilinx, Inc], XCF01SF48 Datasheet - Page 6

• Manufacturer Part Number: XCF01SF48
• Description: Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: XILINX [Xilinx, Inc]

erwise a "01" when an erase or program operation fails. The
Erase/Program (ER/PROG) Status field, IR[4], contains a
logic "1" when the device is busy performing an erase or
programming operation; otherwise, it contains a logic "0".
The ISC Status field, IR[3], contains logic "1" if the device is
currently in In-System Configuration (ISC) mode; otherwise,
Table 6: Platform Flash PROM Boundary Scan Instructions
Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST, SAM-
PLE/PRELOAD, and CLAMP instructions. Each output pin
on the Platform Flash PROM has two register stages which
contribute to the boundary-scan register, while each input
pin has only one register stage. The bidirectional pins have
a total of three register stages which contribute to the
boundary-scan register. For each output pin, the register
DS123 (v2.6) March 14, 2005
Preliminary Product Specification
Notes:
1.
Required Instructions
Optional Instructions
Platform Flash PROM Specific
Instructions
Boundary-Scan Command
TDI
BYPASS
SAMPLE/PRELOAD
EXTEST
CLAMP
HIGHZ
IDCODE
USERCODE
CONFIG
For more information see Initiating FPGA Configuration.
Figure 4: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
Figure 5: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
R
TDI
Reserved
IR[15:9]
Reserved
ISC Error
IR[7:5]
IR[8:7]
XCFxxS IR[7:0]
(hex)
FF
01
00
FA
FC
FE
FD
EE
ISC Status
ER/PROG
IR[6:5]
Error
IR[4]
XCFxxP IR[15:0]
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Platform Flash In-System Programmable Configuration PROMS
ER/PROG
(hex)
FFFF
0001
0000
00FA
00FC
00FE
00FD
00EE
Security
Status
IR[4]
IR[3]
it contains logic "0". The DONE field, IR[2], contains logic
"1" if the sampled design revision has been successfully
programmed; otherwise, a logic "0" indicates incomplete
programming. The remaining bits IR[1:0] are set to '01' as
defined by IEEE Std. 1149.1
.
stage nearest to TDI controls and observes the output state,
and the second stage closest to TDO controls and observes
the High-Z enable state of the output pin. For each input pin,
a single register stage controls and observes the input state
of the pin. The bidirectional pin combines the three bits, the
input stage bit is first, followed by the output stage bit and
finally the output enable stage bit. The output enable stage
bit is closest to TDO.
ISC Status
Enables BYPASS
Enables boundary-scan SAMPLE/PRELOAD operation
Enables boundary-scan EXTEST operation
Enables boundary-scan CLAMP operation
Places all outputs in high-impedance state
simultaneously
Enables shifting out 32-bit IDCODE
Enables shifting out 32-bit USERCODE
Initiates FPGA configuration by pulsing CF pin Low
once. (For the XCFxxP this command also resets the
selected design revision based on either the external
REV_SEL[1:0] pins or on the internal design revision
selection bits.)
IR[3]
IR[2]
0
Instruction Description
(1)
DONE
IR[2]
IR[1:0]
0 1
IR[1:0]
0 1
TDO
TDO
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